3069RF-ZTAT Datasheet, PDF (12/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

6.3.5 Address Output Method....................................................................................... 140
6.4 Basic Bus Interface ........................................................................................................... 142
6.4.1 Overview.............................................................................................................. 142
6.4.2 Data Size and Data Alignment............................................................................. 142
6.4.3 Valid Strobes....................................................................................................... 143
6.4.4 Memory Areas ..................................................................................................... 144
6.4.5 Basic Bus Control Signal Timing ........................................................................ 146
6.4.6 Wait Control ........................................................................................................ 153
6.5 DRAM Interface ............................................................................................................... 155
6.5.1 Overview.............................................................................................................. 155
6.5.2 DRAM Space and RAS Output Pin Settings ....................................................... 155
6.5.3 Address Multiplexing........................................................................................... 156
6.5.4 Data Bus............................................................................................................... 157
6.5.5 Pins Used for DRAM Interface............................................................................ 157
6.5.6 Basic Timing........................................................................................................ 158
6.5.7 Precharge State Control ....................................................................................... 159
6.5.8 Wait Control ........................................................................................................ 160
6.5.9 Byte Access Control and CAS Output Pin........................................................... 161
6.5.10 Burst Operation.................................................................................................... 163
6.5.11 Refresh Control.................................................................................................... 168
6.5.12 Examples of Use .................................................................................................. 172
6.5.13 Usage Notes ......................................................................................................... 176
6.6 Interval Timer ................................................................................................................... 179
6.6.1 Operation ............................................................................................................. 179
6.7 Interrupt Sources............................................................................................................... 184
6.8 Burst ROM Interface......................................................................................................... 184
6.8.1 Overview.............................................................................................................. 184
6.8.2 Basic Timing........................................................................................................ 184
6.8.3 Wait Control ........................................................................................................ 185
6.9 Idle Cycle .......................................................................................................................... 186
6.9.1 Operation ............................................................................................................. 186
6.9.2 Pin States in Idle Cycle ........................................................................................ 189
6.10 Bus Arbiter........................................................................................................................ 190
6.10.1 Operation ............................................................................................................. 190
6.11 Register and Pin Input Timing .......................................................................................... 193
6.11.1 Register Write Timing ......................................................................................... 193
6.11.2 BREQ Pin Input Timing ...................................................................................... 194
Section 7 DMA Controller ................................................................................195
7.1 Overview........................................................................................................................... 195
7.1.1 Features................................................................................................................ 195
7.1.2 Block Diagram ..................................................................................................... 196
7.1.3 Functional Overview............................................................................................ 197
Rev. 5.0, 09/04, page viii of xviii