DRA790 Datasheet, PDF (85/436 Pages) Texas Instruments – Infotainment Applications Processor

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DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
Table 4-15. Universal Serial Bus Signal Descriptions
SIGNAL NAME DESCRIPTION
TYPE
BALL
Universal Serial Bus 1
usb1_dm
USB1 USB2.0 differential signal pair (negative)
IODS
AB7
usb1_dp
USB1 USB2.0 differential signal pair (positive)
IODS
AC6
usb1_drvvbus
usb_rxn0⁽¹⁾
usb_rxp0⁽¹⁾
usb_txn0⁽¹⁾
usb_txp0⁽¹⁾
USB1 Drive VBUS signal
USB1 USB3.0 receiver negative lane
USB1 USB3.0 receiver positive lane
USB1 USB3.0 transmitter negative lane
USB1 USB3.0 transmitter positive lane
O
AD3
IDS
AE5
IDS
AD6
ODS
AE3
ODS
AD4
Universal Serial Bus 2
usb2_dm
USB2 USB2.0 differential signal pair (negative)
IO
AC5
usb2_dp
USB2 USB2.0 differential signal pair (positive)
IO
AB6
usb2_drvvbus
USB2 Drive VBUS signal
O
AA6
Universal Serial Bus 3
usb3_ulpi_d0
USB3 - ULPI 8-bit data bus
IODS
R2, W2
usb3_ulpi_d1
USB3 - ULPI 8-bit data bus
IODS
AA3, R1
usb3_ulpi_d2
USB3 - ULPI 8-bit data bus
IO
AA2, N2
usb3_ulpi_d3
USB3 - ULPI 8-bit data bus
IO
P2, Y4
usb3_ulpi_d4
USB3 - ULPI 8-bit data bus
IO
N1, Y1
usb3_ulpi_d5
USB3 - ULPI 8-bit data bus
IO
P1, Y2
usb3_ulpi_d6
USB3 - ULPI 8-bit data bus
IO
N3, Y6
usb3_ulpi_d7
USB3 - ULPI 8-bit data bus
IO
N4, Y5
usb3_ulpi_nxt
USB3 - ULPI next
I
P3, Y3
usb3_ulpi_dir
USB3 - ULPI bus direction
I
AA1, P4
usb3_ulpi_stp
USB3 - ULPI stop
O
AA4, T5
usb3_ulpi_clk
USB3 - ULPI functional clock
I
AB1, T4
(1) Signals are enabled by selecting the correct field in the PCIE_B1C0_MODE_SEL register. There are no CTRL_CORE_PAD* register
involved.
4.3.15 PCIe
NOTE
For more information, see the Serial Communication Interfaces / PCIe Controllers and the
Shared PHY Component Subsystems / PCIe Shared PHY Susbsytem sections of the device
TRM.
Table 4-16. PCIe Signal Descriptions
SIGNAL NAME
pcie_rxn0
pcie_rxp0
pcie_txn0
pcie_txp0
pcie_rxn1
pcie_rxp1
pcie_txn1
pcie_txp1
DESCRIPTION
PCIe1_PHY_RX Receive Data Lane 0 (negative) - mapped to PCIe_SS1 only.
PCIe1_PHY_RX Receive Data Lane 0 (positive) - mapped to PCIe_SS1 only.
PCIe1_PHY_TX Transmit Data Lane 0 (negative) - mapped to PCIe_SS1 only.
PCIe1_PHY_TX Transmit Data Lane 0 (positive) - mapped to PCIe_SS1 only.
PCIe2_PHY_RX Receive Data Lane 1 (negative) - mapped to either PCIe_SS1
(dual lane- mode) or PCIe_SS2 (single lane- mode)
PCIe2_PHY_RX Receive Data Lane 1 (positive) - mapped to either PCIe_SS1
(dual lane- mode) or PCIe_SS2 (single lane- mode)
PCIe2_PHY_TX Transmit Data Lane 1 (negative) - mapped to either PCIe_SS1
(dual lane- mode) or PCIe_SS2 (single lane- mode)
PCIe2_PHY_TX Transmit Data Lane 1 (positive) - mapped to either PCIe_SS1
(dual lane- mode) or PCIe_SS2 (single lane- mode)
TYPE
IDS
IDS
ODS
ODS
IDS
IDS
ODS
ODS
BALL
AE6
AD7
AE8
AD9
AE5
AD6
AE3
AD4
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Terminal Configuration and Functions
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