DRA790 Datasheet, PDF (218/436 Pages) Texas Instruments – Infotainment Applications Processor

DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
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Table 5-53. Timing Requirements for I²C HS-Mode (I²C3/4/5/6 Only)⁽¹⁾ (continued)
NO. PARAMETER
DESCRIPTION
C_b = 100 pF MAX
MIN
MAX
C_b = 400 pF ⁽²⁾
MIN
MAX
UNIT
4
t_w(SCLL)
LOW period of the SCLH clock
160
320
ns
5
t_w(SCLH)
HIGH period of the SCLH clock
60
120
ns
6
t_{su(SDAV-SCLH)}
Setup time, SDA valid vefore
10
SCL high
10
ns
7
t_h(SCLL-SDAV)
Hold time, SDA valid after SCL
0 ⁽³⁾
70
0 ⁽³⁾
150
ns
low
13
t_{su(SCLH-SDAH)}
Setup time, SCL high before
160
SDA high (for a STOP condition)
160
ns
14 t_w(SP)
15
C_b ⁽²⁾
Pulse duration, spike (must be
0
10
0
10
ns
suppressed)
Capacitive load for SDAH and
100
SCLH lines
400
pF
16 C_b
Capacitive load for SDAH + SDA
400
line and SCLH + SCL line
(1) I²C HS-Mode is only supported on I²C3/4/5/6. I2C HS-Mode is not supported on I²C1/2.
400
pF
(2) For bus line loads C_b between 100 and 400 pF the timing parameters must be linearly interpolated.
(3) A device must internally provide a Data hold time to bridge the undefined part between V_IH and V_IL of the falling edge of the SCLH
signal. An input circuit with a threshold as low as possible for the falling edge of the SCLH signal minimizes this hold time.
I2Ci_SDA
I2Ci_SCL
11
8
4
10
1
7
3
6
5
12
3
2
9
14
13
Stop Start
Repeated
Start
Stop
Figure 5-35. I2C Receive Timing
SPRS906_TIMING_I2C_01
Table 5-54 and Figure 5-36 assume testing over the recommended operating conditions and electrical
characteristic conditions below.
Table 5-54. Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings⁽²⁾
NO. PARAMETER
DESCRIPTION
16 t_c(SCL)
17 t_{su(SCLH-SDAL)}
18 t_h(SDAL-SCLL)
19 t_w(SCLL)
20 t_w(SCLH)
21 t_{su(SDAV-SCLH)}
Cycle time, SCL
Setup time, SCL high before SDA low (for a
repeated START condition)
Hold time, SCL low after SDA low (for a
START and a repeated START condition)
Pulse duration, SCL low
Pulse duration, SCL high
Setup time, SDA valid before SCL high
STANDARD MODE
MIN
MAX
10
4.7
4
4.7
4
250
FAST MODE
MIN
MAX
2.5
0.6
0.6
1.3
0.6
100
UNIT
µs
µs
µs
µs
µs
ns
218 Specifications
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