DRA790 Datasheet, PDF (128/436 Pages) Texas Instruments – Infotainment Applications Processor

DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
www.ti.com
Instance Name
DCAN1
DCAN2
DES3DES
DLL
DLL_AGING
DMM
DPLL_DEBUG
DSP1
DSS
Table 5-5. Maximum Supported Frequency (continued)
Module
Input Clock Name
DCAN1_FCLK
DCAN1_ICLK
DCAN2_FCLK
DCAN2_ICLK
DES_CLK_L3
EMIF_DLL_FCLK
FCLK
DMM_CLK
SYSCLK
DSP1_FICLK
DSS_HDMI_CEC_
CLK
DSS_HDMI_PHY_
CLK
DSS_CLK
HDMI_CLKINP
DSS_L3_ICLK
VIDEO1_CLKINP
VIDEO2_CLKINP
DPLL_DSI1_A_CL
K1
DPLL_DSI1_B_CL
K1
DPLL_DSI1_C_CL
K1
DPLL_HDMI_CLK1
Clock
Type
Func
Int
Func
Int
Int
Func
Int
Int
Int
Int &
Func
Func
Func
Func
Func
Int
Func
Func
Func
Func
Func
Func
Max. Clock
Allowed (MHz)
38.4
266
38.4
266
266
EMIF_DLL_FC
LK
38.4
266
38.4
DSP_CLK
PRCM Clock Name
DCAN1_SYS_CLK
WKUPAON_GICLK
DCAN2_SYS_CLK
L4PER2_L3_GICLK
L4SEC_L3_GICLK
EMIF_DLL_GCLK
L3INSTR_DLL_AGING
_GCLK
EMIF_L3_GICLK
EMU_SYS_CLK
DSP1_GFCLK
Clock Sources
PLL / OSC /
Source Clock
Name
SYS_CLK1
SYS_CLK2
SYS_CLK1
DPLL_ABE_X2_CL
K
SYS_CLK1
CORE_X2_CLK
CORE_X2_CLK
EMIF_DLL_GCLK
SYS_CLK1
DPLL_ABE_X2_CL
K
CORE_X2_CLK
SYS_CLK1
DSP_GFCLK
0.032
HDMI_CEC_GFCLK SYS_CLK1/610
48
HDMI_PHY_GFCLK FUNC_192M_CLK
192
38.4
266
38.4
38.4
209.3
209.3
209.3
185.6
DSS_GFCLK
HDMI_DPLL_CLK
DSS_L3_GICLK
VIDEO1_DPLL_CLK
VIDEO2_DPLL_CLK
N/A
N/A
N/A
N/A
DSS_CLK
SYS_CLK1
SYS_CLK2
CORE_X2_CLK
SYS_CLK1
SYS_CLK2
SYS_CLK1
SYS_CLK2
HDMI_CLK
VIDEO1_CLKOUT1
VIDEO1_CLKOUT3
HDMI_CLK
DPLL_ABE_X2_CL
K
HDMI_CLK
VIDEO1_CLKOUT3
HDMI_CLK
PLL / OSC /
Source Name
OSC1
OSC2
OSC1
DPLL_ABE
OSC1
DPLL_CORE
DPLL_CORE
DPLL_DDR
OSC1
DPLL_ABE
DPLL_CORE
OSC1
DPLL_DSP
OSC1
DPLL_PER
DPLL_PER
OSC1
OSC2
DPLL_CORE
OSC1
OSC2
OSC1
OSC2
DPLL_HDMI
DPLL_VIDEO1
DPLL_VIDEO1
DPLL_HDMI
DPLL_ABE
DPLL_HDMI
DPLL_VIDEO1
DPLL_HDMI
128 Specifications
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