DRA790 Datasheet, PDF (352/436 Pages) Texas Instruments – Infotainment Applications Processor

DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
www.ti.com
• Legacy PCI Interrupts reception (RC) and generation (EP)
• 2 x hardware interrupts per PCIe_SS1and PCIe_SS2 controller mapped via the device Interrupt
Crossbar (IRQ_CROSSBAR) to multiple device host (MPU, DSP, and so forth) interrupt controllers in
the device
• MSIs generation and reception
• PCIe_PHY Loopback in RC mode
For more information, see section PCIe Controller in chapter Serial Communication Interfaces of the
device TRM.
6.11.11 DCAN
The Controller Area Network (CAN) is a serial communications protocol which efficiently supports
distributed real-time applications. CAN has high immunity to electrical interference and the ability to self-
diagnose and repair data errors. In a CAN network, many short messages are broadcast to the entire
network, which provides for data consistency in every node of the system.
The device provides two DCAN interfaces for supporting distributed realtime control with a high level of
security. The DCAN interfaces implement the following features:
• Supports CAN protocol version 2.0 part A, B
• Bit rates up to 1 MBit/s
• 64 message objects
• Individual identifier mask for each message object
• Programmable FIFO mode for message objects
• Programmable loop-back modes for self-test operation
• Suspend mode for debug support
• Software module reset
• Automatic bus on after Bus-Off state by a programmable 32-bit timer
• Direct access to Message RAM during test mode
• CAN Rx/Tx pins are configurable as general-purpose IO pins
• Two interrupt lines (plus additional parity-error interrupts line)
• RAM initialization
• DMA support
For more information, see section DCAN in chapter Serial Communication Interfaces of the device TRM.
6.11.12 GMAC_SW
The three-port gigabit ethernet switch subsystem (GMAC_SW) provides ethernet packet communication
and can be configured as an ethernet switch. It provides the gigabit media independent interface (G/MII) in
MII mode, reduced gigabit media independent interface (RGMII), reduced media independent interface
(RMII), and the management data input output (MDIO) for physical layer device (PHY) management.
The GMAC_SW subsystem provides the following features:
• Two Ethernet ports (port 1 and port 2) with selectable RGMII, RMII, and G/MII (in MII mode only)
interfaces plus internal Communications Port Programming Interface (CPPI 3.1) on port 0
• Synchronous 10/100/1000 Mbit operation
• Wire rate switching (802.1d)
• Non-blocking switch fabric
• Flexible logical FIFO-based packet buffer structure
• Four priority level Quality Of Service (QOS) support (802.1p)
• CPPI 3.1 compliant DMA controllers
• Support for Audio/Video Bridging (P802.1Qav/D6.0)
352 Detailed Description
Copyright © 2016–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DRA790 DRA791 DRA793 DRA797