DRA790 Datasheet, PDF (184/436 Pages) Texas Instruments – Infotainment Applications Processor

DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
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5.9.6.4 DSS
Two Display Parallel Interfaces (DPI) channels are available in DSS named DPI Video Output 2 and DPI
Video Output 3.
NOTE
The DPI Video Output i (i = 2, 3) interface is also referred to as VOUTi.
Every VOUT interface consists of:
• 24-bit data bus (data[23:0])
• Horizontal synchronization signal (HSYNC)
• Vertical synchronization signal (VSYNC)
• Data enable (DE)
• Field ID (FID)
• Pixel clock (CLK)
NOTE
For more information, see the Display Subsystem chapter of the Device TRM.
CAUTION
The I/O Timings provided in this section are valid only if signals within a single
IOSET are used. The IOSETs are defined in Table 5-39.
CAUTION
The I/O Timings provided in this section are valid only for some DSS usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
CAUTION
All pads/balls configured as vouti_* signals must be programmed to use slow
slew rate by setting the corresponding CTRL_CORE_PAD_*[SLEWCONTROL]
register field to SLOW (0b1).
Table 5-37, Table 5-38 and Figure 5-18 assume testing over the recommended operating conditions and
electrical characteristic conditions.
Table 5-37. DPI Video Output i (i = 2, 3) Default Switching Characteristics⁽¹⁾⁽²⁾
NO.
PARAMETE
R
DESCRIPTION
D1 t_c(clk)
Cycle time, output pixel clock vouti_clk
D2 t_w(clkL)
Pulse duration, output pixel clock vouti_clk low
MODE
DPI2/3 in 1.8V mode
DPI2 in 3.3V mode
DPI3 in 3.3V mode
MIN
11.76
MAX
13.33
P × 0.5-
1
UNIT
ns
ns
ns
184 Specifications
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