DRA790 Datasheet, PDF (168/436 Pages) Texas Instruments – Infotainment Applications Processor

DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
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(1) The minimum frequencies on CLKOUT and CLKOUTX2 are assuming M2 = 1.
For M2 > 1, the minimum frequency on these clocks will further scale down by factor of M2.
(2) The maximum frequencies on CLKOUT and CLKOUTX2 are assuming M2 = 1.
(3) The minimum frequency on CLKOUTHIF is assuming M3 = 1. For M3 > 1, the minimum frequency on this clock will further scale down
by factor of M3.
(4) The maximum frequency on CLKOUTHIF is assuming M3 = 1.
(5) Relock time assumes typical operating conditions, 10°C maximum temperature drift.
(6) Bypass mode: f_CLKOUT = F_INP if ulowclken = 0. For more information, see the Device TRM.
Table 5-25. DPLL Type B Characteristics
NAME
f_input
f_internal
f_CLKINPULOW
f_CLKLDOOUT
f_CLKOUT
f_CLKDCOLDO
t_J
t_lock
DESCRIPTION
CLKINP input clock frequency
REFCLK internal reference
clock frequency
CLKINPULOW bypass input
clock frequency
CLKOUTLDO output clock
frequency
CLKOUT output clock
frequency
Internal oscillator (DCO) output
clock frequency
CLKOUTLDO period jitter
CLKOUT period jitter
CLKDCOLDO period jitter
Frequency lock time
p_lock
t_relock-L
p_relock-L
Phase lock time
Relock time—Frequency lock⁽³⁾
(LP relock time from bypass)
Relock time—Phase lock⁽³⁾ (LP
relock time from bypass)
MIN
0.62
0.62
0.001
20⁽¹⁾⁽⁵⁾
20⁽¹⁾⁽⁵⁾
750⁽⁵⁾
1250⁽⁵⁾
–2.5%
TYP
MAX
60
2.5
600
2500⁽²⁾⁽⁵⁾
1450⁽²⁾⁽⁵⁾
1500⁽⁵⁾
2500⁽⁵⁾
UNIT
MHz
MHz
MHz
MHz
MHz
MHz
MHz
COMMENTS
F_INP
[1 / (N + 1)] × F_INP
Bypass mode: f_CLKOUT =
f_CLKINPULOW / (M1 + 1) If
ulowclken = 1⁽⁴⁾
M / (N + 1)] × F_INP × [1 / M2]
(in locked condition)
[M / (N + 1)] × F_INP × [1 / M2]
(in locked condition)
[M / (N + 1)] × F_INP (in locked
condition)
2.5%
The period jitter at the output
clocks is ± 2.5% peak to peak
350 ×
REFCLKs
µs
500 ×
REFCLKs
µs
9 + 30 ×
REFCLKs
µs
9 + 125 ×
REFCLKs
µs
(1) The minimum frequency on CLKOUT is assuming M2 = 1.
For M2 > 1, the minimum frequency on this clock will further scale down by factor of M2.
(2) The maximum frequency on CLKOUT is assuming M2 = 1.
(3) Relock time assumes typical operating conditions, 10°C maximum temperature drift.
(4) Bypass mode: f_CLKOUT = F_INP if ULOWCLKEN = 0. For more information, see the Device TRM.
(5) For output clocks, there are two frequency ranges according to the SELFREQDCO setting. For more information, see the Device TRM.
5.9.4.3.2 DLL Characteristics
Table 5-26 summarizes the DLL characteristics and assumes testing over recommended operating
conditions.
NAME
f_input
t_lock
t_relock
Table 5-26. DLL Characteristics
DESCRIPTION
MIN
Input clock frequency (EMIF_DLL_FCLK)
Lock time
Relock time (a change of the DLL frequency implies that DLL must relock)
TYP
MAX
UNIT
266
MHz
50k
cycles
50k
cycles
168 Specifications
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