DRA790 Datasheet, PDF (390/436 Pages) Texas Instruments – Infotainment Applications Processor

DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
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7.5.2.2.2.6 Crystals/Oscillator
Keep the crystal and its load capacitors close to the USB PHY pins, XI and XO (see Figure 7-25). Note
that frequencies from power sources or large capacitors can cause modulations within the clock and
should not be placed near the crystal. In these instances, errors such as dropped packets occur. A
placeholder for a resistor, in parallel with the crystal, can be incorporated in the design to assist oscillator
startup.
Power is proportional to the current squared. The current is I = C × dv/dt, because dv/dt is a function of
the PHY, current is proportional to the capacitive load. Cutting the load to 1/2 decreases the current by 1/2
and the power to 1/4 of the original value. For more details on crystal selection, see the Selection and
Specification of Crystals for Texas Instruments USB 2.0 Devices (SLLA122).
0.1 µF
X1
Power Pins
XTAL
X0
0.001 µF
USB PHY
SPRS906_PCB_USB20_05
Figure 7-25. Power Supply and Clock Connection to the USB PHY
7.5.2.2.2.7 DP/DM Trace
Place the USB PHY as close as possible to the USB 2.0 connector. The signal swing during high-speed
operation on the DP/DM lines is relatively small (400 mV ± 10%), so any differential noise picked up on
the twisted pair can affect the received signal. When the DP/DM traces do not have any shielding, the
traces tend to behave like an antenna and picks up noise generated by the surrounding components in
the environment. To minimize the effect of this behavior:
• DP/DM traces should always be matched lengths and must be no more than 4 inches in length;
otherwise, the eye opening may be degraded (see Figure 7-26).
• Route DP/DM traces close together for noise rejection on differential signals, parallel to each other and
within two mils in length of each other. The measurement for trace length must be started from
device's balls.
• A high-speed USB connection is made through a shielded, twisted pair cable with a differential
characteristic impedance of 90 Ω ±15%. In layout, the impedance of DP and DM should each be 45 Ω
± 10%.
• DP/DM traces should not have any extra components to maintain signal integrity. For example, traces
cannot be routed to two USB connectors.
390 Applications, Implementation, and Layout
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