DRA790 Datasheet, PDF (326/436 Pages) Texas Instruments – Infotainment Applications Processor

DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
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6.3 MPU
The Cortex®-A15 microprocessor unit (MPU) subsystem serves the applications processing role by
running the high-level operating system (HLOS) and application code.
The MPU subsystem incorporates one Cortex-A15 MPU core (MPU_C0), individual level 1 (L1) caches,
level 2 (L2) cache (MPU_L2CACHE) shared between them, and various other shared peripherals. To aid
software development, the processor core can be kept cache-coherent with the L2 cache.
The MPU subsystem provides a high-performance computing platform with high peak-computing
performance and low memory latency.
The ARM subsystem supports the following key features:
326 Detailed Description
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