DRA790 Datasheet, PDF (423/436 Pages) Texas Instruments – Infotainment Applications Processor

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DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
7.7.2.16.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
Figure 7-60 and Figure 7-61 show the DQS and DQ/DM routing.
DQSn+
DQSn-
Routed Differentially
DQS
n = 0, 1, 2, 3
SPRS906_PCB_DDR3_24
Figure 7-60. DQS Routing With Any Number of Allowed DDR3 Devices
DQ and DM
Dn
n = 0, 1, 2, 3
SPRS906_PCB_DDR3_25
Figure 7-61. DQ/DM Routing With Any Number of Allowed DDR3 Devices
7.7.2.17 Routing Specification
7.7.2.17.1 CK and ADDR_CTRL Routing Specification
Skew within the CK and ADDR_CTRL net classes directly reduces setup and hold margin and, thus, this
skew must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter
traces up to the length of the longest net in the net class and its associated clock. A metric to establish
this maximum length is Manhattan distance. The Manhattan distance between two points on a PCB is the
length between the points when connecting them only with horizontal or vertical segments. A reasonable
trace route length is to within a percentage of its Manhattan distance. CACLM is defined as Clock Address
Control Longest Manhattan distance.
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Applications, Implementation, and Layout 423
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