DRA790 Datasheet, PDF (424/436 Pages) Texas Instruments – Infotainment Applications Processor

DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
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Given the clock and address pin locations on the processor and the DDR3 memories, the maximum
possible Manhattan distance can be determined given the placement. Figure 7-62 and Figure 7-63 show
this distance for four loads and two loads, respectively. It is from this distance that the specifications on
the lengths of the transmission lines for the address bus are determined. CACLM is determined similarly
for other address bus configurations; that is, it is based on the longest net of the CK/ADDR_CTRL net
class. For CK and ADDR_CTRL routing, these specifications are contained in Table 7-34.
(A)
A8
CACLMX
CACLMY
(A)
A8
(A)
A8
(A)
A8
(A)
A8
Rtt
A2
A3
A4
A3
AT
VTT
=
SPRS906_PCB_DDR3_26
A. It is very likely that the longest CK/ADDR_CTRL Manhattan distance will be for Address Input 8 (A8) on the DDR3
memories. CACLM is based on the longest Manhattan distance due to the device placement. Verify the net class that
satisfies this criteria and use as the baseline for CK/ADDR_CTRL skew matching and length control.
The length of shorter CK/ADDR_CTRL stubs as well as the length of the terminator stub are not included in this
length calculation. Non-included lengths are grayed out in the figure.
Assuming A8 is the longest, CALM = CACLMY + CACLMX + 300 mils.
The extra 300 mils allows for routing down lower than the DDR3 memories and returning up to reach A8.
Figure 7-62. CACLM for Four Address Loads on One Side of PCB
424 Applications, Implementation, and Layout
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