DRA790 Datasheet, PDF (142/436 Pages) Texas Instruments – Infotainment Applications Processor

DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
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Instance Name
TIMER10
TIMER11
TIMER12
TIMER13
Table 5-5. Maximum Supported Frequency (continued)
Module
Input Clock Name
TIMER10_ICLK
TIMER10_FCLK
TIMER11_ICLK
TIMER11_FCLK
TIMER12_ICLK
TIMER12_FCLK
TIMER13_ICLK
TIMER13_FCLK
Clock
Type
Int
Func
Int
Func
Int
Func
Int
Func
Max. Clock
Allowed (MHz)
266
100
266
100
38.4
0.032
266
100
PRCM Clock Name
L4PER_L3_GICLK
TIMER10_GFCLK
L4PER_L3_GICLK
TIMER11_GFCLK
WKUPAON_GICLK
OSC_32K_CLK
L4PER3_L3_GICLK
TIMER13_GFCLK
Clock Sources
PLL / OSC /
Source Clock
Name
CORE_X2_CLK
SYS_CLK1
FUNC_32K_CLK
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
CORE_X2_CLK
SYS_CLK1
FUNC_32K_CLK
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
SYS_CLK1
DPLL_ABE_X2_CL
K
RC_CLK
CORE_X2_CLK
SYS_CLK1
FUNC_32K_CLK
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
PLL / OSC /
Source Name
DPLL_CORE
OSC1
OSC1
OSC2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_VIDEO1
DPLL_HDMI
DPLL_CORE
OSC1
OSC1
OSC2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_VIDEO1
DPLL_HDMI
OSC1
DPLL_ABE
RC oscillator
DPLL_CORE
OSC1
OSC1
OSC2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_VIDEO1
DPLL_HDMI
142 Specifications
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