DRA790 Datasheet, PDF (139/436 Pages) Texas Instruments – Infotainment Applications Processor

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DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
Table 5-5. Maximum Supported Frequency (continued)
Module
Instance Name Input Clock Name
SMARTREFLEX_IV
AHD
MCLK
SYSCLK
SMARTREFLEX_M
PU
MCLK
SYSCLK
SPINLOCK
TIMER1
SPINLOCK_ICLK
TIMER1_ICLK
TIMER1_FCLK
TIMER2
TIMER2_ICLK
TIMER2_FCLK
TIMER3
TIMER3_ICLK
TIMER3_FCLK
Clock
Type
Int
Func
Int
Func
Int
Int
Func
Int
Func
Int
Func
Max. Clock
Allowed (MHz)
133
38.4
133
38.4
266
38.4
100
266
100
266
100
PRCM Clock Name
COREAON_L4_GICLK
WKUPAON_ICLK
COREAON_L4_GICLK
WKUPAON_ICLK
L4CFG_L3_GICLK
WKUPAON_GICLK
TIMER1_GFCLK
L4PER_L3_GICLK
TIMER2_GFCLK
L4PER_L3_GICLK
TIMER3_GFCLK
Clock Sources
PLL / OSC /
Source Clock
Name
CORE_X2_CLK
SYS_CLK1
DPLL_ABE_X2_CL
K
CORE_X2_CLK
SYS_CLK1
DPLL_ABE_X2_CL
K
CORE_X2_CLK
SYS_CLK1
DPLL_ABE_X2_CL
K
SYS_CLK1
FUNC_32K_CLK
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
CORE_X2_CLK
SYS_CLK1
FUNC_32K_CLK
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
CORE_X2_CLK
SYS_CLK1
FUNC_32K_CLK
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
PLL / OSC /
Source Name
DPLL_CORE
OSC1
DPLL_ABE
DPLL_CORE
OSC1
DPLL_ABE
DPLL_CORE
OSC1
DPLL_ABE
OSC1
OSC1
OSC2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_VIDEO1
DPLL_HDMI
DPLL_CORE
OSC1
OSC1
OSC2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_VIDEO1
DPLL_HDMI
DPLL_CORE
OSC1
OSC1
OSC2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_VIDEO1
DPLL_HDMI
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Specifications 139