DRA790 Datasheet, PDF (281/436 Pages) Texas Instruments – Infotainment Applications Processor

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DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
5.9.6.21.2.1 Standard JC64 SDR, 8-bit data, half cycle
Table 5-131 and Table 5-132 present Timing requirements and Switching characteristics for MMC2 - Standart SDR in receiver and transmitter
mode (see Figure 5-89 and Figure 5-90).
NO.
SSDR5
SSDR6
SSDR7
SSDR8
PARAMETER
t_{su(cmdV-clkH)}
t_h(clkH-cmdV)
t_su(dV-clkH)
t_h(clkH-dV)
Table 5-131. Timing Requirements for MMC2 - JC64 Standard SDR Mode
DESCRIPTION
Setup time, mmc2_cmd valid before mmc2_clk rising clock edge
Hold time, mmc2_cmd valid after mmc2_clk rising clock edge
Setup time, mmc2_dat[7:0] valid before mmc2_clk rising clock edge
Hold time, mmc2_dat[7:0] valid after mmc2_clk rising clock edge
MIN
13.19
8.4
13.19
8.4
MAX
UNIT
ns
ns
ns
ns
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Specifications 281