DRA790 Datasheet, PDF (258/436 Pages) Texas Instruments – Infotainment Applications Processor

DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
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1
2
miin_rxclk (Input)
miin_rxd3−miin_rxd0,
miin_rxdv, miin_rxer (Inputs)
Figure 5-67. GMAC Receive Interface Timing MIIn operation
SPRS906_TIMING_GMAC_MIIRCV_03
Table 5-91 and Figure 5-68 present timing requirements for GMAC MIIn Transmit 10/100Mbit/s.
Table 5-91. Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit
10/100 Mbits/s
NO.
PARAMETER
1
t_{d(TX_CLK-TXD)}
t_{d(TX_CLK-TX_EN)}
DESCRIPTION
Delay time, miin_txclk to transmit selected signals valid
MIN
MAX
UNIT
0
25
ns
1
miin_txclk (input)
miin_txd3 − miin_txd0,
miin_txen (outputs)
Figure 5-68. GMAC Transmit Interface Timing MIIn operation
SPRS906_TIMING_GMAC_MIITX_04
In Table 5-92 are presented the specific groupings of signals (IOSET) for use with GMAC MII signals.
SIGNALS
mii1_txd3
mii1_txd2
mii1_txd1
mii1_txd0
mii1_rxd3
mii1_rxd2
mii1_rxd1
mii1_rxd0
mii1_col
mii1_rxer
mii1_txer
mii1_txen
mii1_crs
mii1_rxclk
mii1_txclk
mii1_rxdv
mii0_txd3
mii0_txd2
Table 5-92. GMAC MII IOSETs
BALL
E11
A13
A12
B12
B10
A10
F10
E10
E13
B13
F11
D13
C13
B11
C11
D11
IOSET5
MUX
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
BALL
IOSET6
MUX
P2
3
N1
3
258 Specifications
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