DRA790 Datasheet, PDF (291/436 Pages) Texas Instruments – Infotainment Applications Processor

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DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
Table 5-149. Switching Characteristics for MMC3 - SDR12 Mode ⁽²⁾ (continued)
NO. PARAMETER
SDR122 t_w(clkL)
DESCRIPTION
Pulse duration, mmc3_clk low
SDR123 t_d(clkL-cmdV)
Delay time, mmc3_clk falling clock edge to mmc3_cmd transition
SDR124 t_d(clkL-dV)
Delay time, mmc3_clk falling clock edge to mmc3_dat[i:0] transition
(1) P = output mmc3_clk period in ns
(2) i in [i:0] = 7
MIN
0.5 × P-
0.270 ⁽¹⁾
-19.13
-19.13
MAX
16.93
16.93
Table 5-150. Timing Requirements for MMC4 - SDR12 Mode ⁽¹⁾
NO. PARAMETER
SDR125 t_{su(cmdV-clkH)}
SDR126 t_h(clkH-cmdV)
SDR127 t_su(dV-clkH)
SDR128 t_h(clkH-dV)
(1) j in [i:0] = 3
DESCRIPTION
Setup time, mmc4_cmd valid before mmc4_clk rising clock edge
Hold time, mmc4_cmd valid after mmc4_clk rising clock edge
Setup time, mmc4_dat[i:0] valid before mmc4_clk rising clock edge
Hold time, mmc4_dat[i:0] valid after mmc4_clk rising clock edge
MIN
25.99
1.6
25.99
1.6
MAX
Table 5-151. Switching Characteristics for MMC4 - SDR12 Mode ⁽²⁾
NO. PARAMETER
SDR120 fop(clk)
SDR121 t_w(clkH)
DESCRIPTION
Operating frequency, mmc4_clk
Pulse duration, mmc4_clk high
SDR122 t_w(clkL)
Pulse duration, mmc4_clk low
SDR125 t_d(clkL-cmdV)
Delay time, mmc4_clk falling clock edge to mmc4_cmd transition
SDR126 t_d(clkL-dV)
Delay time, mmc4_clk falling clock edge to mmc4_dat[i:0] transition
(1) P = output mmc4_clk period in ns
(2) j in [i:0] = 3
MIN
0.5 × P-
0.270 ⁽¹⁾
0.5 × P-
0.270 ⁽¹⁾
-19.13
-19.13
MAX
24
16.93
16.93
UNIT
ns
ns
ns
UNIT
ns
ns
ns
ns
UNIT
MHz
ns
ns
ns
ns
mmcj_clk
mmcj_cmd
mmcj_dat[i:0]
SDR122
SDR121
SDR120
SDR126
SDR125
SDR128
SDR127
Figure 5-100. MMC/SD/SDIOj in - SDR12 - Receiver Mode
SPRS906_TIMING_MMC3_11
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Specifications 291