English
Language : 

DRA790 Datasheet, PDF (182/436 Pages) Texas Instruments – Infotainment Applications Processor
DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
www.ti.com
Manual IO Timings Modes must be used to guaranteed some IO timings for VIP1. See Table 5-27 Modes Summary for a list of IO timings
requiring the use of Manual IO Timings Modes. See Table 5-35 Manual Functions Mapping for VIN1B (IOSET5) and VIN2B (IOSET2/11) for a
definition of the Manual modes.
Table 5-35 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
BALL
A4
E7
D6
C5
B5
D7
C6
A5
B6
H2
H6
A6
BALL NAME
gpmc_a19
gpmc_a20
gpmc_a21
gpmc_a22
gpmc_a23
gpmc_a24
gpmc_a25
gpmc_a26
gpmc_a27
gpmc_ben0
gpmc_ben1
gpmc_cs1
Table 5-35. Manual Functions Mapping for VIN1B (IOSET5) and VIN2B (IOSET2/11)
VIP_MANUAL10
A_DELAY (ps) G_DELAY (ps)
1600
943
1440
621
1602
1066
1395
983
1571
716
1463
832
1426
1166
1362
1094
1283
809
1978
780
0
0
1411
982
VIP_MANUAL11
A_DELAY (ps) G_DELAY (ps)
2023
477
1875
136
2021
604
1822
519
2045
200
1893
396
1842
732
1797
584
1760
338
2327
389
0
0
1857
536
CFG REGISTER
CFG_GPMC_A19_IN
CFG_GPMC_A20_IN
CFG_GPMC_A21_IN
CFG_GPMC_A22_IN
CFG_GPMC_A23_IN
CFG_GPMC_A24_IN
CFG_GPMC_A25_IN
CFG_GPMC_A26_IN
CFG_GPMC_A27_IN
CFG_GPMC_BEN0_IN
CFG_GPMC_BEN1_IN
CFG_GPMC_CS1_IN
MUXMODE
4
6
-
vin2b_d0
-
vin2b_d1
-
vin2b_d2
-
vin2b_d3
-
vin2b_d4
-
vin2b_d5
-
vin2b_d6
-
vin2b_d7
-
vin2b_hsync1
-
vin2b_de1
vin2b_clk1
vin2b_fld1
-
vin2b_vsync1
Manual IO Timings Modes must be used to guaranteed some IO timings for VIP1. See Table 5-27 Modes Summary for a list of IO timings
requiring the use of Manual IO Timings Modes. See Table 5-36 Manual Functions Mapping for VIN1A (IOSET8/9/10) for a definition of the Manual
modes.
Table 5-36 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
BALL
Y5
Y6
C16
D14
B14
B16
BALL NAME
gpio6_10
gpio6_11
mcasp1_aclkx
mcasp1_axr0
mcasp1_axr1
mcasp1_axr10
Table 5-36. Manual Functions Mapping for VIN1A (IOSET8/9/10)
VIP_MANUAL15
A_DELAY (ps) G_DELAY (ps)
2131
2198
3720
2732
2447
0
3061
0
3113
0
2803
0
VIP_MANUAL16
A_DELAY (ps) G_DELAY (ps)
2170
2180
4106
2448
3042
0
3380
292
3396
304
3362
0
CFG REGISTER
CFG_GPIO6_10_IN
CFG_GPIO6_11_IN
CFG_MCASP1_ACLKX_IN
CFG_MCASP1_AXR0_IN
CFG_MCASP1_AXR1_IN
CFG_MCASP1_AXR10_IN
MUXMODE
7
9
-
vin1a_clk0
-
vin1a_de0
vin1a_fld0
-
vin1a_vsync0
-
vin1a_hsync0
-
vin1a_d13
-
182 Specifications
Submit Documentation Feedback
Product Folder Links: DRA790 DRA791 DRA793 DRA797
Copyright © 2016–2017, Texas Instruments Incorporated