DRA790 Datasheet, PDF (239/436 Pages) Texas Instruments – Infotainment Applications Processor

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9
AHCLKR/X (Falling Edge Polarity)
AHCLKR/X (Rising Edge Polarity)
11
ACLKR/X (CLKRP = CLKXP = 1) ^(A)
ACLKR/X (CLKRP = CLKXP = 0) ^(B)
AFSR/X (Bit Width, 0 Bit Delay)
10
10
12
12
13
13
DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
13
13
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay)
13
AFSR/X (Slot Width, 0 Bit Delay)
13
13
AFSR/X (Slot Width, 1 Bit Delay)
AFSR/X (Slot Width, 2 Bit Delay)
14
15
AXR[n] (Data Out/T ransmit)
A0 A1
A30 A31 B0 B1
B30 B31 C0 C1 C2 C3
C31
SPRS906_TIMING_McASP_02
A. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
receiver is configured for rising edge (to shift data in).
B. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
receiver is configured for falling edge (to shift data in).
Figure 5-54. McASP Output Timing
NOTE
To configure the desired virtual mode the user must set MODESELECT bit and
DELAYMODE bitfield for each corresponding pad control register.
The pad control registers are presented in Table 4-32 and described in Device TRM, Control
Module Chapter.
Table 5-73 through Table 5-80 explain all cases with Virtual Mode Details for McASP1/2/3/4/5/6/7/8 (see
Figure 5-55 through Figure 5-62).
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Specifications 239