DRA790 Datasheet, PDF (404/436 Pages) Texas Instruments – Infotainment Applications Processor

DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
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(1) sdc12, scd21, scd12, sdc21, scd11, sdc11, scd22, and sdc22
7.5.6.1.3 Frequency-domain Specification Guidelines
After the PCB design is finished, the S-parameters of the PCB differential lines will be extracted with a 3D
Maxwell Equation Solver such as the high-frequency structure simulator (HFSS) or equivalent, and
compared to the frequency-domain specification as defined in the section 7 of the MIPI Alliance
Specification for D-PHY Version v1-01-00_r0-03.
If the PCB lines satisfy the frequency-domain specification, the design is finished. Otherwise, the design
needs to be improved.
7.6 Clock Routing Guidelines
7.6.1 Oscillator Ground Connection
Although the impedance of a ground plane is low it is, of course, not zero. Therefore, any noise current in
the ground plane causes a voltage drop in the ground.
Figure 7-36 shows the grounding scheme for high-frequency clock.
Device
xi_oscj
xo_oscj
vssa_oscj
Crystal
Rd
(Optional)
C_f1
C_f2
(1) j in *_osc = 0 or 1
SPRS906_PCB_CLK_OSC_03
Figure 7-36. Grounding Scheme for High-Frequency Clock
7.7 DDR3 Board Design and Layout Guidelines
7.7.1 DDR3 General Board Layout Guidelines
To help ensure good signaling performance, consider the following board design guidelines:
• Avoid crossing splits in the power plane.
• Minimize Vref noise.
• Use the widest trace that is practical between decoupling capacitors and memory module.
• Maintain a single reference.
• Minimize ISI by keeping impedances matched.
• Minimize crosstalk by isolating sensitive bits, such as strobes, and avoiding return path discontinuities.
• Use proper low-pass filtering on the Vref pins.
• Keep the stub length as short as possible.
• Add additional spacing for on-clock and strobe nets to eliminate crosstalk.
• Maintain a common ground reference for all bypass and decoupling capacitors.
• Take into account the differences in propagation delays between microstrip and stripline nets when
evaluating timing constraints.
404 Applications, Implementation, and Layout
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