DRA790 Datasheet, PDF (387/436 Pages) Texas Instruments – Infotainment Applications Processor

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DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
7.5.2.2.2 Specific Guidelines for USB PHY Layout
The following sections describe in detail the specific guidelines for USB PHY Layout.
7.5.2.2.2.1 Analog, PLL, and Digital Power Supply Filtering
To minimize EMI emissions, add decoupling capacitors with a ferrite bead at power supply terminals for
the analog, phase-locked loop (PLL), and digital portions of the chip. Place this array as close to the chip
as possible to minimize the inductance of the line and noise contributions to the system. An analog and
digital supply example is shown in Figure 7-21. In case of multiple power supply pins with the same
function, tie them up to a single low-impedance point in the board and then add the decoupling capacitors,
in addition to the ferrite bead. This array of caps and ferrite bead improve EMI and jitter performance.
Take both EMI and jitter into account before altering the configuration.
Analog
Power Supply
Ferrite Bead
Digital
Power Supply
0.1 µF
Ferrite Bead
AGND
0.01 µF
0.001 µF
1 µF
SoC Board
0.1 µF
0.01 µF
0.001 µF
1 µF
DGND
SPRS906_PCB_USB20_01
Figure 7-21. Suggested Array Capacitors and a Ferrite Bead to Minimize EMI
Consider the recommendations listed below to achieve proper ESD/EMI performance:
• Use a 0.01 μF cap on each cable power VBUS line to chassis GND close to the USB connector pin.
• Use a 0.01 μF cap on each cable ground line to chassis GND next to the USB connector pin.
• If voltage regulators are used, place a 0.01 μF cap on both input and output. This is to increase the
immunity to ESD and reduce EMI. For other requirements, see the device-specific datasheet.
7.5.2.2.2.2 Analog, Digital, and PLL Partitioning
If separate power planes are used, they must be tied together at one point through a low-impedance
bridge or preferably through a ferrite bead. Care must be taken to capacitively decouple each power rail
close to the device. The analog ground, digital ground, and PLL ground must be tied together to the low-
impedance circuit board ground plane.
7.5.2.2.2.3 Board Stackup
Because of the high frequencies associated with the USB, a printed circuit board with at least four layers
is recommended; two signal layers separated by a ground and power layer as shown in Figure 7-22.
Copyright © 2016–2017, Texas Instruments Incorporated
Applications, Implementation, and Layout 387
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