DRA790 Datasheet, PDF (137/436 Pages) Texas Instruments – Infotainment Applications Processor

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DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
Instance Name
McSPI3
McSPI4
MLB_SS
CSI2_0
MMC1
MMC2
MMC3
MMC4
MMU_EDMA
MMU_PCIESS
MPU
MPU_EMU_DBG
OCMC_RAM1
OCMC_ROM
OCP_WP_NOC
OCP2SCP1
OCP2SCP2
OCP2SCP3
Table 5-5. Maximum Supported Frequency (continued)
Module
Input Clock Name
SPI3_ICLK
SPI3_FCLK
SPI4_ICLK
SPI4_FCLK
MLB_L3_ICLK
MLB_L4_ICLK
MLB_FCLK
CTRLCLK
CAL_FCLK
MMC1_CLK_32K
MMC1_FCLK
MMC1_ICLK1
MMC1_ICLK2
MMC2_CLK_32K
MMC2_FCLK
MMC2_ICLK1
MMC2_ICLK2
MMC3_ICLK
MMC3_CLK_32K
MMC3_FCLK
MMC4_ICLK
MMC4_CLK_32K
MMC4_FCLK
MMU1_CLK
MMU2_CLK
MPU_CLK
FCLK
OCMC1_L3_CLK
OCMC_L3_CLK
PICLKOCPL3
L4CFG1_ADAPTE
R_CLKIN
L4CFG2_ADAPTE
R_CLKIN
L4CFG3_ADAPTE
R_CLKIN
Clock
Type
Int
Func
Int
Func
Int
Int
Func
Int &
Func
Int &
Func
Func
Func
Int
Int
Func
Func
Int
Int
Int
Func
Func
Int
Func
Func
Int
Int
Int &
Func
Int
Int
Int
Int
Int
Int
Int
Clock Sources
Max. Clock
Allowed (MHz)
PRCM Clock Name
PLL / OSC /
Source Clock
Name
266
L4PER_L3_GICLK
CORE_X2_CLK
48
PER_48M_GFCLK PER_48M_GFCLK
266
L4PER_L3_GICLK
CORE_X2_CLK
48
PER_48M_GFCLK PER_48M_GFCLK
266
MLB_SHB_L3_GICLK CORE_X2_CLK
133
MLB_SPB_L4_GICLK CORE_X2_CLK
266
MLB_SYS_L3_GFCLK CORE_X2_CLK
96
LVDSRX_96M_GFCLK FUNC_192M_CLK
266
0.032
192
128
266
133
0.032
192
128
266
133
266
0.032
48
192
266
0.032
48
192
266
266
MPU_CLK
CAL_GICLK
L3INIT_32K_GFCLK
MMC1_GFCLK
L3INIT_L3_GICLK
L3INIT_L4_GICLK
L3INIT_32K_GFCLK
MMC2_GFCLK
L3INIT_L3_GICLK
L3INIT_L4_GICLK
L4PER_L3_GICLK
L4PER_32K_GFCLK
MMC3_GFCLK
CORE_ISS_MAIN_
CLK
L3_ICLK
FUNC_32K_CLK
FUNC_192M_CLK
FUNC_256M_CLK
CORE_X2_CLK
CORE_X2_CLK
FUNC_32K_CLK
FUNC_192M_CLK
FUNC_256M_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
FUNC_32K_CLK
FUNC_192M_CLK
L4PER_L3_GICLK
L4PER_32K_GFCLK
MMC4_GFCLK
CORE_X2_CLK
FUNC_32K_CLK
FUNC_192M_CLK
L3MAIN1_L3_GICLK
L3MAIN1_L3_GICLK
MPU_GCLK
CORE_X2_CLK
CORE_X2_CLK
MPU_GCLK
38.4
EMU_SYS_CLK
SYS_CLK1
MPU_GCLK
266
L3MAIN1_L3_GICLK CORE_X2_CLK
266
L3MAIN1_L3_GICLK CORE_X2_CLK
266
L3INSTR_L3_GICLK CORE_X2_CLK
133
L3INIT_L4_GICLK
CORE_X2_CLK
133
L4CFG_L4_GICLK
CORE_X2_CLK
133
L3INIT_L4_GICLK
CORE_X2_CLK
PLL / OSC /
Source Name
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_PER
DPLL_CORE
CM_CORE_AON
OSC1
DPLL_PER
DPLL_PER
DPLL_CORE
DPLL_CORE
OSC1
DPLL_PER
DPLL_PER
DPLL_CORE
DPLL_CORE
DPLL_CORE
OSC1
DPLL_PER
DPLL_CORE
OSC1
DPLL_PER
DPLL_CORE
DPLL_CORE
DPLL_MPU
OSC1
DPLL_MPU
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
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Specifications 137