DRA790 Datasheet, PDF (285/436 Pages) Texas Instruments – Infotainment Applications Processor

www.ti.com
DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
Table 5-137. Switching Characteristics for MMC2 - JC64 High Speed DDR Mode (continued)
NO. PARAMETER
DESCRIPTION
DDR5
DDR6
t_d(clk-cmdV)
t_d(clk-dV)
Delay time, mmc2_clk transition to mmc2_cmd transition
Delay time, mmc2_clk transition to mmc2_dat[7:0] transition
(1) P = output mmc2_clk period in ns
MIN
MAX
UNIT
2.9
7.14
ns
2.9
7.14
ns
mmc2_clk
mmc2_cmd
mmc2_dat[7:0]
DDR8
DDR7
DDR1
DDR2L
DDR3
DDR8
DDR7
DDR2H
DDR4
DDR8
DDR7
DDR7
Figure 5-94. MMC/SD/SDIO in - High Speed DDR JC64 - Receiver Mode
SPRS906_TIMING_MMC2_07
mmc2_clk
mmc2_cmd
mmc2_dat[7:0]
DDR1
DDR5
DDR5
DDR2
DDR2
DDR5
DDR5
DDR6
DDR6
DDR6
DDReMMC6
DDReMMC6
DDR6
Figure 5-95. MMC/SD/SDIO in - High Speed DDR JC64 - Transmitter Mode
SPRS906_TIMING_MMC2_08
NOTE
To configure the desired virtual mode the user must set MODESELECT bit and
DELAYMODE bitfield for each corresponding pad control register.
The pad control registers are presented in Table 4-32 and described in Device TRM, Control
Module Chapter.
Virtual IO Timings Modes must be used to guaranteed some IO timings for MMC2. See Table 5-27 Modes
Summary for a list of IO timings requiring the use of Virtual IO Timings Modes. See Table 5-138 Virtual
Functions Mapping for MMC2 for a definition of the Virtual modes.
Table 5-138 presents the values for DELAYMODE bitfield.
BALL
A6
A4
Table 5-138. Virtual Functions Mapping for MMC2
BALL NAME
gpmc_cs1
gpmc_a19
Delay Mode Value
MMC2_VIRTUAL2
13
13
MUXMODE
1
mmc2_cmd
mmc2_dat4
Copyright © 2016–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DRA790 DRA791 DRA793 DRA797
Specifications 285