DRA790 Datasheet, PDF (254/436 Pages) Texas Instruments – Infotainment Applications Processor

DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
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Table 5-85. Switching Characteristics for ULPI SDR Slave Mode
NO.
US4
US9
PARAMETER
t_d(clkH-stpV)
t_d(clkL-doV)
DESCRIPTION
Delay time, usb_ulpi_clk rising edge high to output
usb_ulpi_stp valid
Delay time, usb_ulpi_clk rising edge high to output
usb_ulpi_d[7:0] valid
MIN
0.44
0.44
MAX
8.35
8.35
UNIT
ns
ns
usbk_ulpi_clk
usbk_ulpi_stp
usbk_ulpi_dir_&_nxt
usbk_ulpi_d[7:0]
US1
US2
US3
US4
US4
US7
Data_IN
US9
US8
US6
US5
US9
Data_OUT
Figure 5-63. HS USB3 ULPI —SDR—Slave Mode—12-pin Mode
SPRS906_TIMING_USB_01
5.9.6.17 PCIe
The device supports connections to PCIe-compliant devices via the integrated PCIe master/slave bus
interface. The PCIe module is comprised of a dual-mode PCIe core and a SerDes PHY. Each PCIe
subsystem controller has support for PCIe Gen-II mode (5.0 Gbps /lane) and Gen-I mode (2.5 Gbps/lane)
(Single Lane and Flexible dual lane configuration).
The device PCIe supports the following features:
• 16-bit operation @250 MHz on PIPE interface (per 16-bit lane)
• Supports 2 ports x 1 lane or 1 port x 2 lanes configuration
• Single virtual channel (VC0), single traffic class (TC0)
• Single function in end-point mode
• Automatic width and speed negotiation
• Max payload: 128 byte outbound, 256 byte inbound
• Automatic credit management
• ECRC generation and checking
• Configurable BAR filtering
• Legacy interrupt reception (RC) and generation (EP)
• MSI generation and reception
• PCI Express Active State Power Management (ASPM) state L0s and L1 (with exceptions)
• All PCI Device Power Management D-states with the exception of D3_cold / L2 state
The PCIe controller on this device conforms to the PCI Express Base 3.0 Specification, revision 1.0 and
the PCI Local Bus Specification, revision 3.0.
NOTE
For more information, see the PCIe Controller section of the Device TRM.
254 Specifications
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