DRA790 Datasheet, PDF (162/436 Pages) Texas Instruments – Infotainment Applications Processor

DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
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Table 5-18 details the OSC0 input clock timing requirements.
Table 5-18. OSC0 Input Clock Timing Requirements
NAME
CK0
1/
t_c(xiosc0)
Frequency, xi_osc0
DESCRIPTION
MIN
TYP
19.2, 20, 27
MAX
CK1
t_w(xiosc0) Pulse duration, xi_osc0 low or high
t_j(xiosc0) Period jitter⁽¹⁾, xi_osc0
t_R(xiosc0) Rise time, xi_osc0
t_F(xiosc0) Fall time, xi_osc0
t_j(xiosc0) Frequency accuracy⁽²⁾, xi_osc0
0.45 ×
t_c(xiosc0)
Ethernet and MLB not used
Ethernet RGMII and RMII
using derived clock
Ethernet MII using derived
clock
MLB using derived clock
0.55 ×
t_c(xiosc0)
0.01 ×
t_c(xiosc0)
5
5
±200
±50
±100
±50
(1) Period jitter is meant here as follows:
– The maximum value is the difference between the longest measured clock period and the expected clock period
– The minimum value is the difference between the shortest measured clock period and the expected clock period
(2) Crystal characteristics should account for tolerance+stability+aging.
UNIT
MHz
ns
ns
ns
ns
ppm
xi_osc0
CK0
CK1
Figure 5-11. xi_osc0 Input Clock
CK1
SPRS906_CLK_05
5.9.4.1.3 Auxiliary Oscillator OSC1 Input Clock
SYS_CLKIN2 is received directly from oscillator OSC1. For more information about SYS_CLKIN2 see
Device TRM, Chapter: Power, Reset, and Clock Management.
5.9.4.1.3.1 OSC1 External Crystal
An external crystal is connected to the device pins. Figure 5-12 describes the crystal implementation.
Device
xi_osc1
xo_osc1
vssa_osc1
Crystal
Rd
(Optional)
C_f1
C_f2
SPRS906_CLK_06
Figure 5-12. Crystal Implementation
162 Specifications
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