DRA790 Datasheet, PDF (320/436 Pages) Texas Instruments – Infotainment Applications Processor

DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
www.ti.com
5.9.6.24 System and Miscellaneous interfaces
The Device includes the following System and Miscellaneous interfaces:
• Sysboot Interface
• System DMA Interface
• Interrupt Controllers (INTC) Interface
5.9.7 Emulation and Debug Subsystem
The Device includes the following Test interfaces:
• IEEE 1149.1 Standard-Test-Access Port (JTAG)
• Trace Port Interface Unit (TPIU)
5.9.7.1 IEEE 1149.1 Standard-Test-Access Port (JTAG)
The JTAG (IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture)
interface is used for BSDL testing and emulation of the device. The trstn pin only needs to be released
when it is necessary to use a JTAG controller to debug the device or exercise the device's boundary scan
functionality. For maximum reliability, the device includes an internal Pulldown (IPD) on the trstn pin to
ensure that trstn is always asserted upon power up and the device's internal emulation logic is always
properly initialized. JTAG controllers from Texas Instruments actively drive trstn high. However, some
third-party JTAG controllers may not drive trstn high but expect the use of a Pullup resistor on trstn. When
using this type of JTAG controller, assert trstn to initialize the device after powerup and externally drive
trstn high before attempting any emulation or boundary-scan operations.
The main JTAG features include:
• 32KB embedded trace buffer (ETB)
• 5-pin system trace interface for debug
• Supports Advanced Event Triggering (AET)
• All processors can be emulated via JTAG ports
• All functions on EMU pins of the device:
– EMU[1:0] - cross-triggering, boot mode (WIR), STM trace
– EMU[4:2] - STM trace only (single direction)
5.9.7.1.1 JTAG Electrical Data/Timing
Table 5-197, Table 5-198 and Figure 5-127 assume testing over the recommended operating conditions
and electrical characteristic conditions below.
Table 5-197. Timing Requirements for IEEE 1149.1 JTAG
NO.
1
1a
1b
3
4
PARAMETER
t_c(TCK)
t_w(TCKH)
t_w(TCKL)
t_su(TDI-TCK)
t_su(TMS-TCK)
t_h(TCK-TDI)
t_h(TCK-TMS)
DESCRIPTION
Cycle time, TCK
Pulse duration, TCK high (40% of t_c)
Pulse duration, TCK low (40% of t_c)
Input setup time, TDI valid to TCK high
Input setup time, TMS valid to TCK high
Input hold time, TDI valid from TCK high
Input hold time, TMS valid from TCK high
MIN
62.29
24.92
24.92
6.23
6.23
31.15
31.15
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
Table 5-198. Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
NO.
2
PARAMETER
t_d(TCKL-TDOV)
DESCRIPTION
Delay time, TCK low to TDO valid
MIN
MAX
UNIT
0
30.5
ns
320 Specifications
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