DRA790 Datasheet, PDF (366/436 Pages) Texas Instruments – Infotainment Applications Processor

DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
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7.2.3.1 PDN Resistance and IR Drop
Lumped methodology consists of grouping all of the power pins on both the PMIC (voltage source) and
processor (current sink) devices. Then the PMIC source is set to an expected Use Case voltage level and
the processor load has its Use Case current sink value set as well. Now the lumped/effective resistance
for the power rail trace/plane routes can be determine based upon the actual layout’s power rail etch wide,
shape, length, via count and placement Figure 7-5 illustrates the pin-grouping/lumped concept.
The lumped methodology consists of importing the PCB layout database (from Cadence Allegro tool or
any other layout design tool) into the static IR drop modeling and simulation tool of preference for the PCB
designer. This is followed by applying the correct PCB stack-up information (thickness, material
properties) of the PCB dielectric and metallization layers. The material properties of dielectric consist of
permittivity (Dk) and loss tangent (Df).
For the conductor layers, the correct conductivity needs to be programmed into the simulation tool. This is
followed by pin-grouping of the power and ground nets, and applying appropriate voltage/current sources.
The current and voltage information can be obtained from the power and voltage specifications of the
device under different operating conditions / Use Cases.
Grouped Power/Ground
pins to create 1 equivalent
resistive branch
Sources
Multiport net
Branch
Port/Pin
Sources
Sinks
Sinks
SPRS906_PCB_PDN_01
Figure 7-5. Pin-grouping concept: Lumped and Distributed Methodologies
7.2.4 Step 4: Frequency Analysis
Delivering low noise voltage sources are very important to allowing a system to operate at the lowest
possible Operational Performance Point (OPP) for any one Use Case. An OPP is a combination of the
supply voltage level and clocking rate for key internal processor domains. A SCH and PCB designed to
provide low noise voltage supplies will then enable the processor to enter optimal OPPs for each Use
Case that in turn will minimize power dissipation and junction temperatures on-die. Therefore, it is a good
engineering practice to perform a Frequency Analysis over the key power domains.
Frequency analysis and design methodology results in a PDN design that minimizes transient noise
voltages at the processor’s input power balls. This allows the processor’s internal transistors to operate
near the minimum specified operating supply voltage levels. To accomplish this one must evaluate how a
voltage supply will change due to impedance variations over frequency. This analysis will focus on the
decoupling capacitor network (VDD_xxx and VSS/Gnd rails) at the load. Sufficient capacitance with a
distribution of self-resonant points will provide for an overall lower impedance vs frequency response for
each power domain.
Decoupling components that are distant from their load’s input power are susceptible to encountering
spreading loop inductance from the PCB design. Early analysis of each key power domain’s frequency
response helps to determine basic decoupling capacitor placement, optimal footprint, layer assignment,
and types needed for minimizing supply voltage noise/fluctuations due to switching and load current
transients.
NOTE
Evaluation of loop inductance values for decoupling capacitors placed ~300mils closer to the
load’s input power balls has shown an 18% reduction in loop inductance due to reduced
distance.
366 Applications, Implementation, and Layout
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