DRA790 Datasheet, PDF (280/436 Pages) Texas Instruments – Infotainment Applications Processor

DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
BALL
U3
V4
V3
V2
W1
V1
U3
V4
V3
V2
W1
V1
V4
V3
V2
W1
V1
BALL NAME
mmc1_clk
mmc1_cmd
mmc1_dat0
mmc1_dat1
mmc1_dat2
mmc1_dat3
mmc1_clk
mmc1_cmd
mmc1_dat0
mmc1_dat1
mmc1_dat2
mmc1_dat3
mmc1_cmd
mmc1_dat0
mmc1_dat1
mmc1_dat2
mmc1_dat3
Table 5-130. Manual Functions Mapping for MMC1
MMC1_MANUAL1
A_DELAY (ps) G_DELAY (ps)
588
0
1000
0
1375
0
1000
0
1000
0
1000
0
MMC1_MANUAL2
A_DELAY (ps)
G_DELAY (ps)
-
-
-
-
-
-
-
-
-
-
-
-
1230
0
520
320
0
0
0
0
56
0
40
0
76
0
83
0
91
0
98
0
99
0
106
0
0
0
51
0
0
0
0
0
0
0
363
0
0
0
199
0
0
0
273
0
CFG REGISTER
CFG_MMC1_CLK_IN
CFG_MMC1_CMD_IN
CFG_MMC1_DAT0_IN
CFG_MMC1_DAT1_IN
CFG_MMC1_DAT2_IN
CFG_MMC1_DAT3_IN
CFG_MMC1_CLK_OUT
CFG_MMC1_CMD_OUT
CFG_MMC1_DAT0_OUT
CFG_MMC1_DAT1_OUT
CFG_MMC1_DAT2_OUT
CFG_MMC1_DAT3_OUT
CFG_MMC1_CMD_OEN
CFG_MMC1_DAT0_OEN
CFG_MMC1_DAT1_OEN
CFG_MMC1_DAT2_OEN
CFG_MMC1_DAT3_OEN
5.9.6.21.2 MMC2 — eMMC
MMC2 interface is compliant with the JC64 eMMC Standard v4.5 and it supports the following eMMC applications:
• Standard JC64 SDR, 8-bit data, half cycle
• High-speed JC64 SDR, 8-bit data, half cycle
• High-speed HS200 JEDS84, 8-bit data, half cycle
• High-speed JC64 DDR, 8-bit data
NOTE
For more information, see the eMMC/SD/SDIO chapter of the Device TRM.
www.ti.com
MUXMODE
0
mmc1_clk
mmc1_cmd
mmc1_dat0
mmc1_dat1
mmc1_dat2
mmc1_dat3
mmc1_clk
mmc1_cmd
mmc1_dat0
mmc1_dat1
mmc1_dat2
mmc1_dat3
mmc1_cmd
mmc1_dat0
mmc1_dat1
mmc1_dat2
mmc1_dat3
280 Specifications
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