DRA790 Datasheet, PDF (103/436 Pages) Texas Instruments – Infotainment Applications Processor

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DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
(1) This clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer to serve
as the internal reference signal. Series termination is recommended (as close to device pin as possible) to improve signal integrity of the
clock input. Any nonmonotonicity in voltage that occurs at the pad loopback clock pin between V_IH and V_IL must be less than V_HYS.
(2) Note that rstoutn is only valid after vddshv3 is valid. If the rstoutn signal will be used as a reset into other devices attached to the SOC, it
must be AND'ed with porz. This will prevent glitches occurring during supply ramping being propagated.
4.3.26.3 System Direct Memory Access (SDMA)
NOTE
For more information, see the DMA Controllers / System DMA section of the device TRM.
Table 4-29. SDMA Signal Descriptions
SIGNAL NAME
dma_evt1
dma_evt2
dma_evt3
dma_evt4
DESCRIPTION
System DMA Event Input 1
System DMA Event Input 2
System DMA Event Input 3
System DMA Event Input 4
4.3.26.4 Interrupt Controllers (INTC)
TYPE
I
I
I
I
NOTE
For more information, see the Interrupt Controllers section of the device TRM.
BALL
G1, L4
H3, H5
H2
H6
Table 4-30. INTC Signal Descriptions
SIGNAL NAME
nmin_dsp
sys_nirq2
sys_nirq1
DESCRIPTION
Non maskable interrupt input, active-low. This pin can be optionally routed to the
DSP NMI input or as generic input to the ARM cores. Note that by default this pin
has an internal pulldown resistor enabled. This internal pulldown should be disabled
or countered by a stronger external pullup resistor before routing to the DSP or
ARM processors.
External interrupt event to any device INTC
External interrupt event to any device INTC
TYPE
I
I
I
4.3.27 Power Supplies
BALL
L24
AC10
AB10
NOTE
For more information, see Power, Reset, and Clock Management / PRCM Subsystem
Environment / External Voltage Inputs section of the device TRM.
SIGNAL NAME
vdd
Table 4-31. Power Supply Signal Descriptions
DESCRIPTION
Core voltage domain supply
TYPE
PWR
BALL
J15, J16, J18, K12,
K18, L12, L17, M11,
M13, M15, M17, N11,
N13, N15, N18, P10,
P12, P14, P16, P18,
R10, R12, R14, R16,
R17, T11, T13, T15,
T17, T9, U11, U13,
U15, U18, U9, V10,
V12, V14, V16, V18,
W10, W12, W14, W16
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Terminal Configuration and Functions 103
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