DRA790 Datasheet, PDF (272/436 Pages) Texas Instruments – Infotainment Applications Processor

DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
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5.9.6.21.1 MMC1—SD Card Interface
MMC1 interface is compliant with the SD Standard v3.01 and it supports the following SD Card
applications:
• Default speed, 4-bit data, SDR, half-cycle
• High speed, 4-bit data, SDR, half-cycle
• SDR12, 4-bit data, half-cycle
• SDR25, 4-bit data, half-cycle
• UHS-I SDR50, 4-bit data, half-cycle
• UHS-I SDR104, 4-bit data, half-cycle
• UHS-I DDR50, 4-bit data
NOTE
For more information, see the eMMC/SD/SDIO chapter of the Device TRM.
5.9.6.21.1.1 Default speed, 4-bit data, SDR, half-cycle
Table 5-116 and Table 5-117 present Timing requirements and Switching characteristics for MMC1 -
Default Speed in receiver and transmitter mode (see Figure 5-75 and Figure 5-76).
Table 5-116. Timing Requirements for MMC1 - SD Card Default Speed Mode
NO.
DSSD5
DSSD6
DSSD7
DSSD8
PARAMETER
t_{su(cmdV-clkH)}
t_h(clkH-cmdV)
t_su(dV-clkH)
t_h(clkH-dV)
DESCRIPTION
Setup time, mmc1_cmd valid before mmc1_clk rising clock edge
Hold time, mmc1_cmd valid after mmc1_clk rising clock edge
Setup time, mmc1_dat[3:0] valid before mmc1_clk rising clock edge
Hold time, mmc1_dat[3:0] valid after mmc1_clk rising clock edge
MIN
5.11
20.46
5.11
20.46
MAX
UNIT
ns
ns
ns
ns
Table 5-117. Switching Characteristics for MMC1 - SD Card Default Speed Mode
NO.
DSSD0
DSSD1
PARAMETER
fop(clk)
t_w(clkH)
DSSD2 t_w(clkL)
DSSD3
DSSD4
t_d(clkL-cmdV)
t_d(clkL-dV)
DESCRIPTION
Operating frequency, mmc1_clk
Pulse duration, mmc1_clk high
Pulse duration, mmc1_clk low
Delay time, mmc1_clk falling clock edge to mmc1_cmd transition
Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition
MIN
0.5 × P-
0.185 ⁽¹⁾
0.5 × P-
0.185 ⁽¹⁾
-14.93
-14.93
MAX
24
14.93
14.93
UNIT
MHz
ns
ns
ns
ns
272 Specifications
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