DRA790 Datasheet, PDF (344/436 Pages) Texas Instruments – Infotainment Applications Processor

DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
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• Programmable divider clock source (2ⁿ, where n = [0:8])
• Dedicated input trigger for capture mode and dedicated output trigger/PWM signal
• Dedicated GP output signal for using the TIMERi_GPO_CFG signal
• On-the-fly read/write register (while counting)
• 1-ms tick with 32.768-Hz functional clock generated (only TIMER1, TIMER2, and TIMER10)
For more information, see section Timers of the device TRM.
6.11.3.2 32-kHz Synchronized Timer (COUNTER_32K)
The 32-kHz synchronized timer (COUNTER_32K) is a 32-bit counter clocked by the falling edge of the 32-
kHz system clock.
The main features of the 32-kHz synchronized timer controller are:
• L4 slave interface (OCP) support:
– 32-bit data bus width
– 32-/16-bit access supported
– 8-bit access not supported
– 16-bit address bus width
– Burst mode not supported
– Write nonposted transaction mode not supported
• Only read operations are supported on the module registers; no write operation is supported (no
error/no action on write).
• Free-running 32-bit upward counter
• Start and keep counting after power-on reset
• Automatic roll over to 0; highest value reached: 0xFFFF FFFF
• On-the-fly read (while counting)
For more information, see section Timers of the device TRM.
6.11.3.3 Watchdog Timer
The device includes one instance of the 32-bit watchdog timer: WD_TIMER2.
The watchdog timer is an upward counter capable of generating a pulse on the reset pin and an interrupt
to the device system modules following an overflow condition. The WD_TIMER2 timer serves resets to the
PRCM module (its interrupt outputs are unused).
WD_TIMER2 is located in the PD_WKUPAON power domain, and can run when the device is in lowest
power state (all power domains are off except always-on (AON) and WKUP).
The watchdog timer can be accessed, loaded, and cleared by registers through the L4_WKUP interface.
The watchdog timer has the 32-kHz clock for its timer clock input. WD_TIMER2 directly generates a warm
reset condition on overflow.
WD_TIMER2 connects to a single target agent port on the L4_WKUP interconnect.
The main features of the watchdog timer controllers are:
• L4 slave interface support:
– 32-bit data bus width
– 32-/16-bit access supported
– 8-bit access not supported
– 11-bit address bus width
– Burst mode not supported
– Write nonposted mode supported
• Free-running 32-bit upward counter
344 Detailed Description
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