DRA790 Datasheet, PDF (185/436 Pages) Texas Instruments – Infotainment Applications Processor

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DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
Table 5-37. DPI Video Output i (i = 2, 3) Default Switching Characteristics⁽¹⁾⁽²⁾ (continued)
NO.
PARAMETE
R
DESCRIPTION
MODE
MIN MAX UNIT
D3 t_w(clkH)
Pulse duration, output pixel clock vouti_clk high
P × 0.5-
ns
1
D5 t_d(clk-ctlV)
Delay time, output pixel clock vouti_clk transition to output DPI2 (vin2a_fld0 clock -2.5
2.5
ns
data vouti_d[23:0] valid
reference)
D6 t_d(clk-dV)
Delay time, output pixel clock vouti_clk transition to output DPI2 (vin2a_fld0 clock -2.5
2.5
ns
control signals vouti_vsync, vouti_hsync, vouti_de, and
reference)
vouti_fld valid
D5 t_d(clk-ctlV)
Delay time, output pixel clock vouti_clk transition to output
data vouti_d[23:0] valid
DPI3
-2.5
2.5
ns
D6 t_d(clk-dV)
Delay time, output pixel clock vouti_clk transition to output
control signals vouti_vsync, vouti_hsync, vouti_de, and
vouti_fld valid
DPI3
-2.5
2.5
ns
(1) P = output vouti_clk period in ns.
(2) All pads/balls configured as vouti_* signals must be programmed to use slow slew rate by setting the corresponding
CTRL_CORE_PAD_*[SLEWCONTROL] register field to SLOW (0b1).
(3) SERDES transceivers may be sensitive to the jitter profile of vouti_clk. See Application Note SPRAC62 for additional guidance.
Table 5-38. DPI Video Output i (i = 2, 3) Alternate Switching Characteristics⁽²⁾
NO.
PARAMETE
R
DESCRIPTION
D1 t_c(clk)
Cycle time, output pixel clock vouti_clk
D2 t_w(clkL)
D3 t_w(clkH)
D5 t_d(clk-ctlV)
D6 t_d(clk-dV)
D5 t_d(clk-ctlV)
D6 t_d(clk-dV)
Pulse duration, output pixel clock vouti_clk low
Pulse duration, output pixel clock vouti_clk high
Delay time, output pixel clock vouti_clk transition to output
data vouti_d[23:0] valid
Delay time, output pixel clock vouti_clk transition to output
control signals vouti_vsync, vouti_hsync, vouti_de, and
vouti_fld valid
Delay time, output pixel clock vouti_clk transition to output
data vouti_d[23:0] valid
Delay time, output pixel clock vouti_clk transition to output
control signals vouti_vsync, vouti_hsync, vouti_de, and
vouti_fld valid
MODE
MIN MAX
DPI2/3 in 1.8V mode
6.06
DPI2 in 3.3V mode
DPI3 in 3.3V mode
13.33
P × 0.5-
1 ⁽¹⁾
P × 0.5-
1 ⁽¹⁾
DPI2 (vin2a_fld0 clock 1.51 4.55
reference)
DPI2 (vin2a_fld0 clock 1.51 4.55
reference)
DPI3
1.51 4.55
DPI3
1.51 4.55
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
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Specifications 185