DRA790 Datasheet, PDF (273/436 Pages) Texas Instruments – Infotainment Applications Processor

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DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
(1) P = output mmc1_clk period in ns
DSSD2
DSSD1
DSSD0
mmc1_clk
DSSD6
mmc1_cmd
mmc1_dat[3:0]
DSSD5
DSSD8
DSSD7
SPRS906_TIMING_MMC1_01
Figure 5-75. MMC/SD/SDIO in - Default Speed - Receiver Mode
DSSD2
DSSD1
DSSD0
mmc1_clk
DSSD3
mmc1_cmd
mmc1_dat[3:0]
DSSD4
SPRS906_TIMING_MMC1_02
Figure 5-76. MMC/SD/SDIO in - Default Speed - Transmitter Mode
5.9.6.21.1.2 High speed, 4-bit data, SDR, half-cycle
Table 5-118 and Table 5-119 present Timing requirements and Switching characteristics for MMC1 - High
Speed in receiver and transmitter mode (see Figure 5-77 and Figure 5-78).
Table 5-118. Timing Requirements for MMC1 - SD Card High Speed
NO.
HSSD3
HSSD4
HSSD7
HSSD8
PARAMETER
t_{su(cmdV-clkH)}
t_h(clkH-cmdV)
t_su(dV-clkH)
t_h(clkH-dV)
DESCRIPTION
MIN
Setup time, mmc1_cmd valid before mmc1_clk rising clock edge
5.3
Hold time, mmc1_cmd valid after mmc1_clk rising clock edge
2.6
Setup time, mmc1_dat[3:0] valid before mmc1_clk rising clock edge
5.3
Hold time, mmc1_dat[3:0] valid after mmc1_clk rising clock edge
2.6
MAX
UNIT
ns
ns
ns
ns
Table 5-119. Switching Characteristics for MMC1 - SD Card High Speed
NO. PARAMETER
HSSD1 fop(clk)
HSSD2H t_w(clkH)
HSSD2L t_w(clkL)
HSSD5
HSSD6
t_d(clkL-cmdV)
t_d(clkL-dV)
DESCRIPTION
Operating frequency, mmc1_clk
Pulse duration, mmc1_clk high
Pulse duration, mmc1_clk low
Delay time, mmc1_clk falling clock edge to mmc1_cmd transition
Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition
MIN
0.5 × P-
0.185 ⁽¹⁾
0.5 × P-
0.185 ⁽¹⁾
-7.6
-7.6
MAX
48
3.6
3.6
UNIT
MHz
ns
ns
ns
ns
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Specifications 273