DRA790 Datasheet, PDF (220/436 Pages) Texas Instruments – Infotainment Applications Processor

DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
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NOTE
For more information, see the HDQ / 1-Wire section of the Device TRM.
5.9.6.11.1 HDQ / 1-Wire — HDQ Mode
Table 5-55 and Table 5-56 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see Figure 5-37, Figure 5-38, Figure 5-39 and Figure 5-40).
Table 5-55. HDQ/1-Wire Timing Requirements—HDQ Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
1
t_CYCH
2
t_HW1
3
t_HW0
4
t_RSPS
Read bit window timing
Read one data valid after HDQ low
Read zero data hold after HDQ low
Response time from HDQ slave device⁽¹⁾
190
250
µs
32⁽²⁾
66⁽²⁾
µs
70⁽²⁾
145⁽²⁾
µs
190
320
µs
(1) Defined by software.
(2) If the HDQ slave device drives a logic-low state after tHW0 maximum, it can be interpreted as a break pulse. For more information see
"HDQ / 1-Wire Switching Characteristics - HDQ Mode" and the HDQ/1-Wire chapter of the TRM.
Table 5-56. HDQ / 1-Wire Switching Characteristics - HDQ Mode
NO.
PARAMETER
DESCRIPTION
MIN
5
t_B
Break timing
190
6
t_BR
Break recovery time
40
7
t_CYCD
Write bit windows timing
190
8
t_DW1
Write one data valid after HDQ low
0.5
9
t_DW0
Write zero data hold after HDQ low
86
MAX
50
145
UNIT
µs
µs
µs
µs
µs
HDQ
t_B
t_BR
SPRS906_TIMING_HDQ1W_01
Figure 5-37. HDQ Break and Break Recovery Timing — HDQ Interface Writing to Slave
HDQ
t_HW1
t_HW0
t_CYCH
Figure 5-38. Device HDQ Interface Bit Read Timing (Data)
SPRS906_TIMING_HDQ1W_02
HDQ
t_DW1
t_DW0
t_CYCD
SPRS906_TIMING_HDQ1W_03
Figure 5-39. Device HDQ Interface Bit Write Timing (Command / Address or Data)
220 Specifications
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