DRA790 Datasheet, PDF (266/436 Pages) Texas Instruments – Infotainment Applications Processor

DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
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(1) For RGMII, transmit selected signals include: rgmiin_txd[3:0] and rgmiin_txctl.
(2) RGMII0 requires that the 4 data pins rgmii0_txd[3:0] and rgmii0_txctl have their board propagation delays matched within 50pS of
rgmii0_txc.
(3) RGMII1 requires that the 4 data pins rgmii1_txd[3:0] and rgmii1_txctl have their board propagation delays matched within 50pS of
rgmii1_txc.
rgmiin_txc^(A)
[internal delay enabled]
1
4
2
3
4
rgmiin_txd[3:0]^(B)
rgmiin_txctl^(B)
1st Half-byte 2nd Half-byte
TXEN
TXERR
5
6
SPRS906_TIMING_GMAC_RGMIITX_09
A. TXC is delayed internally before being driven to the rgmiin_txc pin. This internal delay is always enabled.
B. Data and control information is transmitted using both edges of the clocks. rgmiin_txd[3:0] carries data bits 3-0 on the
rising edge of rgmiin_txc and data bits 7-4 on the falling edge of rgmiin_txc. Similarly, rgmiin_txctl carries TXEN on
rising edge of rgmiin_txc and TXERR of falling edge of rgmiin_txc.
Figure 5-73. GMAC Transmit Interface Timing RGMIIn operation
In Table 5-107 are presented the specific groupings of signals (IOSET) for use with GMAC RGMII signals.
SIGNALS
rgmii1_txd3
rgmii1_txd2
rgmii1_txd1
rgmii1_txd0
rgmii1_rxd3
rgmii1_rxd2
rgmii1_rxd1
rgmii1_rxd0
rgmii1_rxctl
rgmii1_txc
rgmii1_txctl
rgmii1_rxc
rgmii0_txd3
rgmii0_txd2
rgmii0_txd1
rgmii0_txd0
rgmii0_rxd3
rgmii0_rxd2
rgmii0_rxd1
rgmii0_rxd0
rgmii0_txc
rgmii0_rxctl
Table 5-107. GMAC RGMII IOSETs
BALL
C11
B12
A12
A13
B13
E13
C13
D13
F11
B11
D11
E11
IOSET3
MUX
3
3
3
3
3
3
3
3
3
3
3
3
BALL
IOSET4
MUX
P4
0
P3
0
R2
0
R1
0
N1
0
P1
0
N3
0
N4
0
T4
0
P2
0
266 Specifications
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