DRA790 Datasheet, PDF (209/436 Pages) Texas Instruments – Infotainment Applications Processor

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DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
gpmc_fclk
gpmc_clk
gpmc_csi
gpmc_a27
gpmc_a[10:1]
gpmc_ben0
gpmc_ben1
gpmc_advn_ale
gpmc_wen
gpmc_ad[15:0]
FA9
FA10
FA10
FA3
FA12
FA25
FA29
Valid Address (LSB)
FA1
Address (MSB)
FA0
FA0
FA27
FA28
Data OUT
gpmc_waitj
DIR
OUT
GPMC_12
Figure 5-30. GPMC / Multiplexed NOR Flash - Asynchronous Write - Single Word Timing⁽¹⁾
(1) In “gpmc_csi”, i = 0 to 7. In “gpmc_waitj”, j = 0 to 1.
(2) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal
direction on the GPMC data bus.
5.9.6.8.3 GPMC/NAND Flash Interface Asynchronous Timing
CAUTION
The I/O Timings provided in this section are valid only for some GPMC usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
Table 5-49 and Table 5-50 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see Figure 5-31, Figure 5-32, Figure 5-33 and Figure 5-34).
NO.
GNF12
-
-
Table 5-49. GPMC/NAND Flash Interface Timing Requirements
PARAMETER
DESCRIPTION
MIN
t_acc(DAT)
t_su(DV-OEH)
Data maximum access time (GPMC_FCLK Cycles)
Setup time, read gpmc_ad[15:0] valid before
1.9
gpmc_oen_ren high
t_h(OEH-DV)
Hold time, read gpmc_ad[15:0] valid after
1
gpmc_oen_ren high
MAX
J ⁽¹⁾
UNIT
cycles
ns
ns
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Specifications 209