DRA790 Datasheet, PDF (130/436 Pages) Texas Instruments – Infotainment Applications Processor

DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
www.ti.com
Table 5-5. Maximum Supported Frequency (continued)
Module
Instance Name Input Clock Name
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPMC
HDMI PHY
HDQ1W
GPIO4_ICLK
GPIO4_DBCLK
PIDBCLK
GPIO5_ICLK
GPIO5_DBCLK
PIDBCLK
GPIO6_ICLK
GPIO6_DBCLK
PIDBCLK
GPIO7_ICLK
GPIO7_DBCLK
PIDBCLK
GPIO8_ICLK
GPIO8_DBCLK
PIDBCLK
GPMC_FCLK
DSS_HDMI_PHY_
CLK
HDQ1W_ICLK
I2C1
I2C2
I2C3
I2C4
I2C5
I2C6
IEEE1500_2_OCP
HDQ1W_FCLK
I2C1_ICLK
I2C1_FCLK
I2C2_ICLK
I2C2_FCLK
I2C3_ICLK
I2C3_FCLK
I2C4_ICLK
I2C4_FCLK
I2C5_ICLK
I2C5_FCLK
I2C6_ICLK
I2C6_FCLK
PI_L3CLK
IPU1
IPU1_GFCLK
IPU2
KBD
IPU2_GFCLK
KBD_FCLK
PICLKKBD
KBD_ICLK
PICLKOCP
Clock
Type
Int
Func
Func
Int
Func
Func
Int
Func
Func
Int
Func
Func
Int
Func
Func
Int
Func
Int &
Func
Func
Int
Func
Int
Func
Int
Func
Int
Func
Int
Func
Int
Func
Int &
Func
Int &
Func
Int &
Func
Func
Func
Int
Int
Max. Clock
Allowed (MHz)
266
0.032
0.032
266
0.032
0.032
266
0.032
0.032
266
0.032
0.032
266
0.032
0.032
266
38.4
PRCM Clock Name
L4PER_L3_GICLK
GPIO_GFCLK
GPIO_GFCLK
L4PER_L3_GICLK
GPIO_GFCLK
GPIO_GFCLK
L4PER_L3_GICLK
GPIO_GFCLK
GPIO_GFCLK
L4PER_L3_GICLK
GPIO_GFCLK
GPIO_GFCLK
L4PER_L3_GICLK
GPIO_GFCLK
GPIO_GFCLK
L3MAIN1_L3_GICLK
HDMI_PHY_GFCLK
Clock Sources
PLL / OSC /
Source Clock
Name
CORE_X2_CLK
FUNC_32K_CLK
CORE_X2_CLK
FUNC_32K_CLK
CORE_X2_CLK
FUNC_32K_CLK
CORE_X2_CLK
FUNC_32K_CLK
CORE_X2_CLK
FUNC_32K_CLK
CORE_X2_CLK
FUNC_192M_CLK
266
L4PER_L3_GICLK
CORE_X2_CLK
12
PER_12M_GFCLK FUNC_192M_CLK
266
L4PER_L3_GICLK
CORE_X2_CLK
96
PER_96M_GFCLK FUNC_192M_CLK
266
L4PER_L3_GICLK
CORE_X2_CLK
96
PER_96M_GFCLK FUNC_192M_CLK
266
L4PER_L3_GICLK
CORE_X2_CLK
96
PER_96M_GFCLK FUNC_192M_CLK
266
L4PER_L3_GICLK
CORE_X2_CLK
96
PER_96M_GFCLK FUNC_192M_CLK
266
IPU_L3_GICLK
CORE_X2_CLK
96
IPU_96M_GFCLK FUNC_192M_CLK
266
L4PER2_L3_GICLK CORE_X2_CLK
96
IPU_96M_GFCLK FUNC_192M_CLK
266
L3INIT_L3_GICLK
CORE_X2_CLK
425.6
425.6
0.032
0.032
38.4
38.4
IPU1_GFCLK
DPLL_ABE_X2_CL
K
CORE_IPU_ISS_B
OOST_CLK
IPU2_GFCLK
CORE_IPU_ISS_B
OOST_CLK
WKUPAON_SYS_GFC WKUPAON_32K_G
LK
FCLK
WKUPAON_SYS_GFC
LK
WKUPAON_GICLK
SYS_CLK1
WKUPAON_GICLK DPLL_ABE_X2_CL
K
PLL / OSC /
Source Name
DPLL_CORE
OSC1
DPLL_CORE
OSC1
DPLL_CORE
OSC1
DPLL_CORE
OSC1
DPLL_CORE
OSC1
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_ABE
DPLL_CORE
DPLL_CORE
OSC1
OSC1
DPLL_ABE
130 Specifications
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