DRA790 Datasheet, PDF (230/436 Pages) Texas Instruments – Infotainment Applications Processor

DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
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Table 5-64. Switching Characteristics for QSPI (continued)
NO. PARAMETER DESCRIPTION
Q2 t_w(SCLKL)
Pulse duration, sclk low
MODE
MIN
Y × P-1
(1)
MAX
UNIT
ns
Q3 t_w(SCLKH)
Pulse duration, sclk high
Y × P-1
ns
(1)
Q4 t_d(CS-SCLK)
Delay time, sclk falling edge to cs active edge, CS3:0 Default Timing Mode -M × P- -M ×
ns
1.6 ⁽²⁾ P+2.6
(3)
(2) (3)
Q5 t_d(SCLK-CS)
Delay time, sclk falling edge to cs inactive edge,
CS3:0
Default Timing Mode N × P- N ×
ns
1.6 ⁽²⁾ P+2.6
(3)
(2) (3)
Q6 t_d(SCLK-D0)
Q7
t_ena(CS-D0LZ)
Q8
t_dis(CS-D0Z)
Q9 t_d(SCLK-D0)
Delay time, sclk falling edge to d[0] transition
Default Timing Mode
-1.6
2.6
ns
Enable time, cs active edge to d[0] driven (lo-z)
-P-3.5 -P+2.5 ns
Disable time, cs active edge to d[0] tri-stated (hi-z)
-P-2.5 -P+2.0 ns
Delay time, sclk first falling edge to first d[0] transition PHA=0 Only, Default
-1.6
2.6
ns
Timing Mode
(1) The Y parameter is defined as follows:
If DCLK_DIV is 0 or ODD then, Y equals 0.5.
If DCLK_DIV is EVEN then, Y equals (DCLK_DIV/2) / (DCLK_DIV+1).
For best performance, it is recommended to use a DCLK_DIV of 0 or ODD to minimize the duty cycle distortion. The HSDIVIDER on
CLKOUTX2_H13 output of DPLL_PER can be used to achieve the desired clock divider ratio. All required details about clock division
factor DCLK_DIV can be found in the device-specific Technical Reference Manual.
(2) P = SCLK period.
(3) M=QSPI_SPI_DC_REG.DDx + 1 when Clock Mode 0.
M=QSPI_SPI_DC_REG.DDx when Clock Mode 3.
N = 2 when Clock Mode 0.
N = 3 when Clock Mode 3.
PHA=1
cs
Q4
POL=1
sclk
Q1
Q3 Q2
Q5
Q15
Q14
Q7
d[0]
d[3:1]
Q6
Q6
Command Command
Bit n-1
Bit n-2
Q12 Q13
Read Data
Bit 1
Read Data
Bit 0
Q14
Q15
Q12 Q13
Read Data
Bit 1
Read Data
Bit 0
Figure 5-49. QSPI Read (Clock Mode 3)
SPRS85v_TIMING_OSPI1_01
230 Specifications
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