DRA790 Datasheet, PDF (5/436 Pages) Texas Instruments – Infotainment Applications Processor

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DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
2 Revision History
Changes from August 16, 2016 to February 28, 2017 (from * Revision (August 2016) to A Revision)
Page
• Updated features list ................................................................................................................. 1
• Added device hex codes to Table 3-1 ............................................................................................. 6
• Added "Related Products" section.................................................................................................. 7
• Updated chapter with template alignment and content enhancement ....................................................... 11
• Updated DSIS Description for "blank" in Section 4.2........................................................................... 11
• Updated VIP IOSETs and ball numbers in Table 4-2 and in Table 4-21 .................................................... 68
• Added missing ball numbers for alternative signals to the corresponding signal description tables ..................... 72
• Added note for RESETOUTn connection in Table 4-28 ...................................................................... 102
• Changed GPMC 1 Load / 5 Load to Default Mode / Alternate Mode in Table 4-28 ...................................... 102
• Fixed typos and clean-up in Section 5.4 ....................................................................................... 123
• Updated boot voltages for VD_DSP............................................................................................. 126
• Updated IQ1833 Buffers DC Electrical Characteristics Table ............................................................... 148
• Updated rstoutn timing in figure Power-Up Sequencing to start after Note 9.............................................. 156
• Updated chapter with template alignment and content enhancement ...................................................... 159
• Added DSS_VIRTUAL1 and MMC2_VIRTUAL2 options to the Timing Chapter Section 5.9.6 ......................... 169
• Changed GPMC 1 Load / 5 Load to Default Mode / Alternate Mode in Table 5-27 ...................................... 169
• Updated VIN Data Manual Timing Mode descriptions in Table 5-27 ....................................................... 169
• Updated Timing specification values for VIP, DSS VOUT, GPMC, McSPI, QSPI, McASP, Ethernet and MMC1-4
Interfaces ........................................................................................................................... 171
• Updated VIP IOSETs and ball numbers in Table 5-29 ....................................................................... 173
• Added missing balls for vin1b in IOSET7 in Table 5-29 ...................................................................... 173
• Fixed missing ball for vin1a_d15 in Vin1 IOSET9 ............................................................................. 173
• Updated Manual Modes for VIP, DSS, MMC and PRU-ICSS Interfaces................................................... 178
• Added DSS clock jitter footnotes on Table 5-37 and Table 5-38............................................................ 184
• Removed DPI2 (xref_clk2 clock reference) IOSET2 from Timing tables................................................... 184
• Updated are Virtual Mode Case Details for McASP2 when AXR(Inputs)/CLKX/FSX in 80MHz and non-80MHz
operation. .......................................................................................................................... 240
• Fixed typo in naming of figures McASP1-8 for SYNC Mode in Table 5-5.................................................. 249
• Removed McASP "ahclkx" signals from Table 5-81 and Table 5-82 ....................................................... 249
• Updated ball number for RMII_MHZ_50_CLK in Table 5-100 ............................................................... 262
• Removed 1149.7 (cJTAG) support .............................................................................................. 322
• Updated chapter with template alignment and content enhancement ...................................................... 341
• Updated Recommended PDN and Decoupling Characteristics table....................................................... 377
• Added information in Section 7.3.5.............................................................................................. 377
• Updated capacitor value in diagram for PLL supply decoupling ............................................................ 387
• Updated impedance tolerance to USB3.0 in Table 7-10 ..................................................................... 395
• Updated symbolization in Printed Device Reference Figure 8-1 and Nomenclature Description Table 8-1........... 429
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Revision History
5