DRA790 Datasheet, PDF (324/436 Pages) Texas Instruments – Infotainment Applications Processor

DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
www.ti.com
6 Detailed Description
6.1 Description
The DRA79x processor is offered in a 538-ball, 17×17-mm, 0.65-mm ball pitch (0.8mm spacing rules can
be used on signals) with Via Channel™ Array (VCA) technology, ball grid array (BGA) package.
The architecture is designed to deliver high-performance concurrencies for automotive applications in a
cost-effective solution, providing full scalability from the DRA75x ("Jacinto 6 EP" and "Jacinto 6 Ex"),
DRA74x "Jacinto 6" and DRA72x "Jacinto 6 Eco" family of infotainment processors.
Programmability is provided by a single-core ARM Cortex-A15 RISC CPU with Neon™ extensions and a
TI C66x VLIW floating-point DSP core. The ARM processor lets developers keep control functions
separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity
of the system software.
Additionally, TI provides a complete set of development tools for the ARM, and DSP, including C
compilers and a debugging interface for visibility into source code execution.
The DRA79x Jacinto 6 Entry processor family is qualified according to the AEC-Q100 standard.
The device features are simplified power supply rail mapping which enables lower cost PMIC solutions.
6.2 Functional Block Diagram
Figure 6-1 is functional block diagram for the device.
324 Detailed Description
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