DRA790 Datasheet, PDF (303/436 Pages) Texas Instruments – Infotainment Applications Processor

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DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
1
2
4
3
MDIO_CLK
4
Figure 5-120. PRU-ICSS MDIO_CLK Timing
SPRS91x_TIMING_PRU_MII_RT_02
Table 5-174. PRU-ICSS MDIO Switching Characteristics – MDIO_DATA
NO. PARAMETER
DESCRIPTION
MIN
1
t_d(MDC-MDIO)
Delay time, MDC high to MDIO valid
0
MAX UNIT
390 ns
1
MDIO_CLK (Output)
MDIO_DATA (Output)
Figure 5-121. PRU-ICSS MDIO_DATA Timing – Output Mode
5.9.6.23.3.2 PRU-ICSS MII_RT Electrical Data and Timing
SPRS91x_TIMING_PRU_MII_RT_03
NOTE
In order to guarantee the MII_RT IO timing values published in the device data manual, the
ICSS_CLK clock must be configured for 200MHz (default value) and the TX_CLK_DELAY
bitfield in the PRUSS_MII_RT_TXCFG0/1 register must be set to 6h (non-default value).
Table 5-175. PRU-ICSS MII_RT Timing Requirements – MII[x]_RXCLK
NO. PARAMETER
1
t_{c(RX_CLK)}
2
t_{w(RX_CLKH)}
3
t_{w(RX_CLKL)}
DESCRIPTION
Cycle time, RX_CLK
Pulse duration, RX_CLK high
Pulse duration, RX_CLK low
SPEED
10 Mbps
100 Mbps
10 Mbps
100 Mbps
10 Mbps
100 Mbps
MIN
399.96
39.996
140
14
140
14
MAX
400.04
40.004
260
26
260
26
UNIT
ns
ns
ns
ns
ns
ns
1
2
4
3
MII_RXCLK
Figure 5-122. PRU-ICSS MII[x]_RXCLK Timing
4
SPRS91x_TIMING_PRU_MII_RT_04
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