DRA790 Datasheet, PDF (192/436 Pages) Texas Instruments – Infotainment Applications Processor

DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
In are presented the specific groupings of signals (IOSET) for use with HDMI.
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NOTE
For more information, see the High-Definition Multimedia Interface chapter of the device
TRM
5.9.6.6 CSI2
NOTE
For more information, see the Camera Serial Interface 2 CAL Bridge chapter of the device
TRM
The camera adaptation layer (CAL) deals with the processing of the pixel data coming from an external
image sensor, data from memory. The CAL is a key component for the following multimedia applications:
camera viewfinder, video record, and still image capture. The CAL has two serial camera interfaces
(primary and secondary):
• The primary serial interface (CSI2 Port A) is compliant with MIPI CSI-2 protocol with four data lanes.
5.9.6.6.1 CSI-2 MIPI D-PHY—1.5 V and 1.8 V
The CSI-2 port A is compliant with the MIPI D-PHY RX specification v1.00.00 and the MIPI CSI-2
specification v1.00, with 4 data differential lanes plus 1 clock differential lane in synchronous mode,
double data rate:
• 1.5 Gbps (750 MHz) @OPP_NOM for each lane.
The CSI-2 port B is compliant with the MIPI D-PHY RX specification v1.00.00 and the MIPI CSI-2
specification v1.00, with 2 data lanes plus 1 clock lane (differential) in synchronous mode, double data
rate:
• 1.5 Gbps (750 MHz) @OPP_NOM for each lane, in synchronous mode.
5.9.6.7 EMIF
The device has a dedicated interface to DDR3 and DDR3L SDRAM. It supports JEDEC standard
compliant DDR3 and DDR3L SDRAM devices with the following features:
• 16-bit or 32-bit data path to external SDRAM memory
• Memory device capacity: 128Mb, 256Mb, 512Mb, 1Gb, 2Gb, 4Gb and 8Gb devices
• One interface with associated DDR3/DDR3L PHYs
NOTE
For more information, see the EMIF Controller section of the Device TRM.
5.9.6.8 GPMC
The GPMC is the unified memory controller that interfaces external memory devices such as:
• Asynchronous SRAM-like memories and ASIC devices
• Asynchronous page mode and synchronous burst NOR flash
• NAND flash
NOTE
For more information, see the General-Purpose Memory Controller section of the Device
TRM.
192 Specifications
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