DRA790 Datasheet, PDF (341/436 Pages) Texas Instruments – Infotainment Applications Processor

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DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
• 64 DMA channels
– Channels triggered by either:
• Event synchronization
• Manual synchronization (CPU write to event set register)
• Chain synchronization (completion of one transfer triggers another transfer)
– Support for programmable DMA Channel to PaRAM mapping
• 8 Quick DMA (QDMA) channels
– QDMA channels are triggered automatically upon writing to PaRAM set entry
– Support for programmable QDMA channel to PaRAM mapping
• 512 PaRAM sets
– Each PaRAM set can be used for a DMA channel, QDMA channel, or link set
• 2 transfer controllers/event queues
– 16 event entries per event queue
• Interrupt generation based on:
– Transfer completion
– Error conditions
• Debug visibility
– Queue water marking/threshold
– Error and status recording to facilitate debug
• Memory protection support
– Proxied memory protection for TR submission
– Active memory protection for accesses to PaRAM and registers
Each EDMATC has the following features:
• Supports 2-dimensional (2D) transfers with independent indexes on source and destination (EDMACC
manages the 3rd dimension)
• Up to 4 in-flight transfer requests (TR)
• Programmable priority levels
• Support for increment or constant addressing mode transfers
• Interrupt and error support
• Supports only little-endian operation in this device
• Memory mapped register (MMR) bit fields are fixed position in 32-bit MMR
For more information chapter EDMA Controller of the device TRM.
6.11 Peripherals
6.11.1 VIP
The VIP module provides video capture functions for the device. VIP incorporates a multi-channel raw
video parser, various video processing blocks, and a flexible Video Port Direct Memory Access (VPDMA)
engine to store incoming video in various formats. The device uses a single instantiation of the VIP
module giving the ability of capturing up to two video streams.
A VIP module includes the following main features:
• Two independently configurable external video input capture slices (Slice 0 and Slice 1) each of which
has two video input ports, Port A and Port B, where Port A can be configured as a 24/16/8-bit port, and
Port B is a fixed 8-bit port.
• Each video Port A can be operated as a port with clock independent input channels (with interleaved or
separated Y/C data input). Embedded sync and external sync modes are supported for all input
configurations.
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