DRA790 Datasheet, PDF (378/436 Pages) Texas Instruments – Infotainment Applications Processor

DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
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Whenever one SMPS supplies multiple SoC voltage domains from a common power rail, the most
stringent PDN guideline across the voltage domains being combined should be applied to the common
power rail.
It is possible that some voltage domains on the device are unused in some systems. In such cases, to
ensure device reliability, it is still required that the supply pins for the specific voltage domains are
connected to some core power supply output.
These unused supplies though can be combined with any of the core supplies that are used (active) in the
system. e.g. if the DSP domain is not used, it can be combined with the CORE domain, thereby having a
single power supply driving the combined CORE and DSP domains.
For the combined rail, the following relaxations do apply:
• The AVS voltage of active voltage domain in the combined rail needs to be used to set the power
supply
• The decoupling capacitance should be set according to the active voltage domain in the combined rail
• The PDN guideline should be set according to the active voltage domain in the combined rail
Table 7-4 illustrates the approved and validated power supply connections to the Device for the SMPS
outputs of the TPS656919 PMIC.
Table 7-4. TPS65919 Power Supply Connections⁽¹⁾
SMPS
Valid Combination
TPS65919 Current
Limitation^{(2) (3)}
SMPS1
VD_CORE
3.5A
SMPS2
Free (DDR Memory)
3.5A
SMPS3
VD_DSP
3A
SMPS4
VDDS18V
1.5A
(1) Power consumption is highly application-specific. Separate analysis must be performed to ensure output current ratings (average and
peak) is within the limits of the PMIC for all rails of the device.
(2) Refer to the PMIC data manual for the latest TPS65919 specifications.
(3) A product’s maximum ambient temperature, thermal system design & heat spreading performance could limit the maximum power
dissipation below the full PMIC capacity in order to not exceed recommended SoC max Tj.
Table 7-5 illustrates the approved and validated power supply connections to the Device for the SMPS
outputs of the LP8733 PMIC.
Table 7-5. LP8733 Power Supply Connections
SMPS
Valid Combination
LP8733 Current Limitation⁽¹⁾
(2)
SMPS1
VD_CORE
3A
SMPS2
VD_DSP
3A
(1) Refer to the LP8733 Data Manual for exact current rating limitations, including assumed VIN and other parameters. Values provided in
this table are for comparison purposes.
(2) Highly application-specific. Separate analysis must be performed to ensure average and peak power is within the limits of the PMIC.
7.3.6 DPLL Voltage Requirement
The voltage input to the DPLLs has a low noise requirement. Board designs should supply these voltage
inputs with a low noise LDO to ensure they are isolated from any potential digital switching noise. The
TPS65919 PMIC LDOLN output is specifically designed to meet this low noise requirement.
378 Applications, Implementation, and Layout
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