DRA790 Datasheet, PDF (143/436 Pages) Texas Instruments – Infotainment Applications Processor

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DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
Instance Name
TIMER14
TIMER15
TIMER16
TPCC
TPTC1
TPTC2
UART1
UART2
UART3
Table 5-5. Maximum Supported Frequency (continued)
Module
Input Clock Name
TIMER14_ICLK
TIMER14_FCLK
TIMER15_ICLK
TIMER15_FCLK
TIMER16_ICLK
TIMER16_FCLK
TPCC_GCLK
TPTC0_GCLK
TPTC1_GCLK
UART1_FCLK
UART1_ICLK
UART2_FCLK
UART2_ICLK
UART3_FCLK
UART3_ICLK
Clock
Type
Int
Func
Int
Func
Int
Func
Int
Int
Int
Func
Int
Func
Int
Func
Int
Max. Clock
Allowed (MHz)
266
100
266
100
266
100
266
266
266
48
266
48
266
48
266
PRCM Clock Name
L4PER3_L3_GICLK
TIMER14_GFCLK
L4PER3_L3_GICLK
TIMER15_GFCLK
L4PER3_L3_GICLK
TIMER16_GFCLK
L3MAIN1_L3_GICLK
L3MAIN1_L3_GICLK
L3MAIN1_L3_GICLK
UART1_GFCLK
L4PER_L3_GICLK
UART2_GFCLK
L4PER_L3_GICLK
UART3_GFCLK
L4PER_L3_GICLK
Clock Sources
PLL / OSC /
Source Clock
Name
CORE_X2_CLK
SYS_CLK1
FUNC_32K_CLK
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
CORE_X2_CLK
SYS_CLK1
FUNC_32K_CLK
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
CORE_X2_CLK
SYS_CLK1
FUNC_32K_CLK
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
FUNC_192M_CLK
CORE_X2_CLK
FUNC_192M_CLK
CORE_X2_CLK
FUNC_192M_CLK
CORE_X2_CLK
PLL / OSC /
Source Name
DPLL_CORE
OSC1
OSC1
OSC2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_VIDEO1
DPLL_HDMI
DPLL_CORE
OSC1
OSC1
OSC2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_VIDEO1
DPLL_HDMI
DPLL_CORE
OSC1
OSC1
OSC2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_VIDEO1
DPLL_HDMI
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
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Specifications 143