DRA790 Datasheet, PDF (167/436 Pages) Texas Instruments – Infotainment Applications Processor

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DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
Table 5-23. DPLL Control Type (continued)
DPLL NAME
DPLL_GMAC
DPLL_HDMI
DPLL_IVA
DPLL_MPU
DPLL_PER
APLL_PCIE
DPLL_PCIE_REF
DPLL_USB
DPLL_USB_OTG_SS
DPLL_VIDEO1
DPLL_DDR
DPLL_GPU
(1) DPLL is in the always-on domain.
(2) DPLL is not controlled by the PRCM.
TYPE
Table 5-24 (Type A)
Table 5-25 (Type B)
Table 5-24 (Type A)
Table 5-24 (Type A)
Table 5-24 (Type A)
Table 5-24 (Type A)
Table 5-25 (Type B)
Table 5-25 (Type B)
Table 5-25 (Type B)
Table 5-24 (Type A)
Table 5-24 (Type A)
Table 5-24 (Type A)
CONTROLLED BY PRCM
Yes⁽¹⁾
No⁽²⁾
Yes⁽¹⁾
Yes⁽¹⁾
Yes⁽¹⁾
Yes⁽¹⁾
Yes⁽¹⁾
Yes⁽¹⁾
No⁽²⁾
No⁽²⁾
Yes⁽¹⁾
Yes⁽¹⁾
Table 5-24 and Table 5-25 summarize the DPLL characteristics and assume testing over recommended
operating conditions.
NAME
f_input
f_internal
f_CLKINPHIF
f_CLKINPULOW
f_CLKOUT
f_CLKOUTx2
f_CLKOUTHIF
f_CLKDCOLDO
t_lock
p_lock
t_relock-L
p_relock-L
t_relock-F
p_relock-F
Table 5-24. DPLL Type A Characteristics
DESCRIPTION
CLKINP input frequency
Internal reference frequency
CLKINPHIF input frequency
MIN
TYP
0.032
0.15
10
MAX
52
52
1400
UNIT
MHz
MHz
MHz
CLKINPULOW input frequency
0.001
600 MHz
CLKOUT output frequency
20⁽¹⁾
CLKOUTx2 output frequency
40⁽¹⁾
20⁽³⁾
CLKOUTHIF output frequency
40⁽³⁾
DCOCLKLDO output
frequency
40
Frequency lock time
Phase lock time
Relock time—Frequency
lock⁽⁵⁾ (LP relock time from
bypass)
Relock time—Phase lock⁽⁵⁾
(LP relock time from bypass)
Relock time—Frequency
lock⁽⁵⁾ (fast relock time from
bypass)
Relock time—Phase lock⁽⁵⁾
(fast relock time from bypass)
1400⁽²⁾ MHz
2200⁽²⁾
1400⁽⁴⁾
2200⁽⁴⁾
MHz
MHz
MHz
2800
6 + 350 ×
REFCLK
6 + 500 ×
REFCLK
6 + 70 ×
REFCLK
6 + 120 ×
REFCLK
3.55 + 70 ×
REFCLK
3.55 + 120 ×
REFCLK
MHz
µs
µs
µs
µs
µs
µs
COMMENTS
F_INP
REFCLK
F_INPHIF
Bypass mode: f_CLKOUT =
f_CLKINPULOW / (M1 + 1) if
ulowclken = 1⁽⁶⁾
[M / (N + 1)] × F_INP × [1 / M2]
(in locked condition)
2 × [M / (N + 1)] × F_INP × [1 /
M2] (in locked condition)
F_INPHIF / M3 if clkinphifsel = 1
2 × [M / (N + 1)] × F_INP × [1 /
M3] if clkinphifsel = 0
2 × [M / (N + 1)] × F_INP (in
locked condition)
DPLL in LP relock time:
lowcurrstdby = 1
DPLL in LP relock time:
lowcurrstdby = 1
DPLL in fast relock time:
lowcurrstdby = 0
DPLL in fast relock time:
lowcurrstdby = 0
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Specifications 167