DRA790 Datasheet, PDF (129/436 Pages) Texas Instruments – Infotainment Applications Processor

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DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
Table 5-5. Maximum Supported Frequency (continued)
Module
Instance Name Input Clock Name
DSS DISPC
LCD1_CLK
LCD2_CLK
LCD3_CLK
F_CLK
EFUSE_CTRL_CU
ST
ocp_clk
sys_clk
ELM
EMIF_OCP_FW
EMIF_PHY1
EMIF1
GMAC_SW
ELM_ICLK
L3_CLK
EMIF_PHY1_FCLK
EMIF1_ICLK
CPTS_RFT_CLK
GPIO1
MAIN_CLK
MHZ_250_CLK
MHZ_5_CLK
MHZ_50_CLK
RMII1_MHZ_50_CL
K
RMII2_MHZ_50_CL
K
GPIO1_ICLK
GPIO2
GPIO3
GPIO1_DBCLK
GPIO2_ICLK
GPIO2_DBCLK
GPIO3_ICLK
GPIO3_DBCLK
Clock
Type
Func
Func
Func
Func
Int
Func
Int
Int
Func
Int
Func
Int
Func
Func
Func
Func
Func
Int
Func
Int
Func
Int
Func
Clock Sources
Max. Clock
Allowed (MHz)
PRCM Clock Name
PLL / OSC /
Source Clock
Name
209.3
N/A
DPLL_DSI1_A_CL
K1
DSS_CLK
209.3
N/A
DPLL_DSI1_B_CL
K1
DSS_CLK
209.3
N/A
DPLL_DSI1_C_CL
K1
DSS_CLK
209.3
N/A
DPLL_DSI1_A_CL
K1
DPLL_DSI1_B_CL
K1
DPLL_DSI1_C_CL
K1
DSS_CLK
DPLL_HDMI_CLK1
133
CUSTEFUSE_L4_GICL CORE_X2_CLK
K
38.4
CUSTEFUSE_SYS_GF
SYS_CLK1
CLK
266
L4PER_L3_GICLK
CORE_X2_CLK
266
EMIF_L3_GICLK
CORE_X2_CLK
DDR
EMIF_PHY_GCLK EMIF_PHY_GCLK
266
EMIF_L3_GICLK
CORE_X2_CLK
266
GMAC_RFT_CLK PER_ABE_X1_GF
CLK
VIDEO1_CLK
HDMI_CLK
CORE_X2_CLK
125
GMAC_MAIN_CLK GMAC_250M_CLK
250
GMII_250MHZ_CLK GMII_250MHZ_CL
K
5
RGMII_5MHZ_CLK GMAC_RMII_HS_C
LK
50
RMII_50MHZ_CLK GMAC_RMII_HS_C
LK
50
RMII_50MHZ_CLK GMAC_RMII_HS_C
LK
50
RMII_50MHZ_CLK GMAC_RMII_HS_C
LK
38.4
WKUPAON_GICLK
SYS_CLK1
DPLL_ABE_X2_CL
K
0.032
WKUPAON_SYS_GFC WKUPAON_32K_G
LK
FCLK
266
L4PER_L3_GICLK
CORE_X2_CLK
0.032
GPIO_GFCLK
FUNC_32K_CLK
266
L4PER_L3_GICLK
CORE_X2_CLK
0.032
GPIO_GFCLK
FUNC_32K_CLK
PLL / OSC /
Source Name
See DSS data in
the rows above
DPLL_CORE
OSC1
DPLL_CORE
DPLL_CORE
DPLL_DDR
DPLL_CORE
DPLL_ABE
DPLL_VIDEO1
DPLL_HDMI
DPLL_CORE
DPLL_GMAC
DPLL_GMAC
DPLL_GMAC
DPLL_GMAC
DPLL_GMAC
DPLL_GMAC
OSC1
DPLL_ABE
OSC1
DPLL_CORE
OSC1
DPLL_CORE
OSC1
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Specifications 129