DRA790 Datasheet, PDF (146/436 Pages) Texas Instruments – Infotainment Applications Processor

DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
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Table 5-6. LVCMOS DDR DC Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
NOM
MAX
UNIT
Z_O
Output impedance (drive
strength)
l[2:0] = 000
(Imp80)
80
Ω
l[2:0] = 001
60
(Imp60)
l[2:0] = 010
48
(Imp48)
l[2:0] = 011
40
(Imp40)
l[2:0] = 100
34
(Imp34)
Single-Ended Receiver Mode
V_IH
High-level input threshold
DDR3/DDR3L
V_IL
Low-level input threshold
DDR3/DDR3L
V_CM
Input common-mode voltage
VREF+0.1
-0.2
VREF -
10%vdds
VDDS+0.2
V
VREF-0.1
V
VREF+
V
10%vdds
C_PAD
Pad capacitance (including package capacitance)
Signal Names in MUXMODE 0 (Differential Signals): ddr1_ck, ddr1_nck, ddr1_dqs[3:0], ddr1_dqsn[3:0]
3
pF
Bottom Balls: AD21 / AE21 / AD22 / AE22 / Y24 / Y25 / V24 / V25 / R24 / R25;
Driver Mode
V_OH
V_OL
C_PAD
Z_O
High-level output threshold (I_OH = 0.1 mA)
Low-level output threshold (I_OL = 0.1 mA)
Pad capacitance (including package capacitance)
Output impedance (drive
strength)
l[2:0] = 000
(Imp80)
0.9 × VDDS
V
0.1 × VDDS
V
3
pF
80
Ω
l[2:0] = 001
60
(Imp60)
l[2:0] = 010
48
(Imp48)
l[2:0] = 011
40
(Imp40)
l[2:0] = 100
34
(Imp34)
Single-Ended Receiver Mode
V_IH
High-level input threshold
DDR3/DDR3L
V_IL
Low-level input threshold
DDR3/DDR3L
V_CM
Input common-mode voltage
VREF+0.1
-0.2
VREF -
10%vdds
VDDS+0.2
V
VREF-0.1
V
VREF+
V
10%vdds
C_PAD
Pad capacitance (including package capacitance)
Differential Receiver Mode
3
pF
V_SWING
V_CM
Input voltage swing
Input common-mode voltage
DDR3/DDR3L
0.2
VREF -
10%vdds
vdds+0.4
V
VREF+
V
10%vdds
C_PAD
Pad capacitance (including package capacitance)
3
pF
(1) VDDS in this table stands for corresponding power supply (i.e. vdds_ddr1). For more information on the power supply name and the
corresponding ball, see Table 4-1, POWER [11] column.
(2) VREF in this table stands for corresponding Reference Power Supply (i.e. ddr1_vref0). For more information on the power supply name
and the corresponding ball, see Table 4-1, POWER [11] column.
(3) For more information on the I/O cell configurations (i[2:0], sr[1:0]), see the Chapter Control Module of the Device TRM.
146 Specifications
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