DRA790 Datasheet, PDF (236/436 Pages) Texas Instruments – Infotainment Applications Processor

DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
(3) R = ACLKR/X period in ns.
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1
AHCLKR/X (Falling Edge Polarity)
AHCLKR/X (Rising Edge Polarity)
ACLKR/X (CLKRP = CLKXP = 0) ^(A)
ACLKR/X (CLKRP = CLKXP = 1) ^(B)
AFSR/X (Bit Width, 0 Bit Delay)
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay)
AFSR/X (Slot Width, 0 Bit Delay)
AFSR/X (Slot Width, 1 Bit Delay)
AFSR/X (Slot Width, 2 Bit Delay)
2
2
3
6
5
4
4
AXR[n] (Data In/Receive)
8
7
A0 A1
A30 A31 B0 B1
B30 B31 C0 C1 C2 C3
C31
SPRS906_TIMING_McASP_01
A. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
receiver is configured for falling edge (to shift data in).
B. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
receiver is configured for rising edge (to shift data in).
Figure 5-53. McASP Input Timing
CAUTION
The I/O Timings provided in this section are valid only for some McASP usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
Table 5-70, Table 5-71, Table 5-72 and Figure 5-54 present Switching Characteristics Over
Recommended Operating Conditions for McASP1 to McASP8.
236 Specifications
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