DRA790 Datasheet, PDF (127/436 Pages) Texas Instruments – Infotainment Applications Processor

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DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
Table 5-4 describes the standard processor clocks speed characteristics vs OPP of the device.
Table 5-4. Supported OPP vs Max Frequency ⁽²⁾
DESCRIPTION
OPP_NOM
Max Freq. (MHz)
VD_CORE
MPU_CLK
800
CORE_IPUx_CLK
212.8
L3_CLK
266
DDR3 / DDR3L
667 (DDR-1333)
VD_DSP
DSP_CLK
600
(1) N/A in this table stands for Not Applicable.
(2) Maximum supported frequency is limited according to the Device Speed Grade (see Table 5-1).
OPP_HIGH
Max Freq. (MHz)
N/A
N/A
N/A
N/A
750
5.5.3 Maximum Supported Frequency
Device modules either receive their clock directly from an external clock input, directly from a PLL, or from
a PRCM. Table 5-5 lists the clock source options for each module on this device, along with the maximum
frequency that module can accept. To ensure proper module functionality, the device PLLs and dividers
must be programmed not to exceed the maximum frequencies listed in this table.
Table 5-5. Maximum Supported Frequency
Module
Instance Name Input Clock Name
AES1
AES2
ATL
AES1_L3_CLK
AES2_L3_CLK
ATL_ICLK_L3
ATLPCLK
COUNTER_32K
COUNTER_32K_F
CLK
COUNTER_32K_IC
LK
CTRL_MODULE_B L3INSTR_TS_GCL
ANDGAP
K
CTRL_MODULE_C L4CFG_L4_GICLK
ORE
CTRL_MODULE_ WKUPAON_GICLK
WKUP
Clock
Type
Int
Int
Int
Func
Func
Int
Int
Int
Int
Max. Clock
Allowed (MHz)
266
266
266
266
0.032
38.4
4.8
133
38.4
PRCM Clock Name
L4SEC_L3_GICLK
L4SEC_L3_GICLK
ATL_L3_GICLK
ATL_GFCLK
FUNC_32K_CLK
WKUPAON_GICLK
L3INSTR_TS_GCLK
L4CFG_L4_GICLK
WKUPAON_GICLK
Clock Sources
PLL / OSC /
Source Clock
Name
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
PER_ABE_X1_GF
CLK
FUNC_32K_CLK
HDMI_CLK
VIDEO1_CLK
SYS_CLK1/610
SYS_CLK1
DPLL_ABE_X2_CL
K
SYS_CLK1
DPLL_ABE_X2_CL
K
CORE_X2_CLK
SYS_CLK1
DPLL_ABE_X2_CL
K
PLL / OSC /
Source Name
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_ABE
OSC1
DPLL_HDMI
DPLL_VIDEO1
OSC1
OSC1
DPLL_ABE
OSC1
DPLL_ABE
DPLL_CORE
OSC1
DPLL_ABE
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Specifications 127