DRA790 Datasheet, PDF (219/436 Pages) Texas Instruments – Infotainment Applications Processor

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DRA790, DRA791
DRA793, DRA797
SPRS968A – AUGUST 2016 – REVISED FEBRUARY 2017
Table 5-54. Switching Characteristics Over Recommended Operating Conditions for I2C Output
Timings⁽²⁾ (continued)
NO. PARAMETER
DESCRIPTION
22 t_h(SCLL-SDAV)
23 t_w(SDAH)
24 t_r(SDA)
Hold time, SDA valid after SCL low (for I2C
bus devices)
Pulse duration, SDA high between STOP and
START conditions
Rise time, SDA
STANDARD MODE
MIN
MAX
0
3.45
4.7
1000
FAST MODE
MIN
MAX
0
0.9
1.3
20 + 0.1C_b
(1) (3)
300⁽³⁾
UNIT
µs
µs
ns
25 t_r(SCL)
Rise time, SCL
1000
20 + 0.1C_b
(1) (3)
300⁽³⁾
ns
26 t_f(SDA)
Fall time, SDA
300
20 + 0.1C_b
(1) (3)
300⁽³⁾
ns
27 t_f(SCL)
Fall time, SCL
300
20 + 0.1C_b
(1) (3)
300⁽³⁾
ns
28 t_{su(SCLH-SDAH)}
Setup time, SCL high before SDA high (for
STOP condition)
4
0.6
µs
29 C_p
Capacitance for each I2C pin
10
10
pF
(1) C_b = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
(2) Software must properly configure the I2C module registers to achieve the timings shown in this table. See the Device TRM for details.
(3) These timings apply only to I2C1 and I2C2. I2C3, I2C4, I2C5 and I2C6 use standard LVCMOS buffers to emulate open-drain buffers
and their rise/fall times should be referenced in the device IBIS model.
NOTE
I2C emulation is achieved by configuring the LVCMOS buffers to output Hi-Z instead of
driving high when transmitting logic-1.
I2Ci_SDA
I2Ci_SCL
26
23
19
25
21
20
16
18
27
22
18
17
24
28
Stop Start
Repeated
Start
Stop
Figure 5-36. I2C Transmit Timing
SPRS906_TIMING_I2C_02
In are presented the specific groupings of signals (IOSET) for use with I2C1/2/3/4/5.
5.9.6.11 HDQ1W
The module is intended to work with both HDQ and 1-Wire protocols. The protocols use a single wire to
communicate between the master and the slave. The protocols employ an asynchronous return to one
mechanism where, after any command, the line is pulled high.
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Specifications 219